On Tue, Nov 9, 2010 at 1:48 PM, Zhe Wang <[email protected]> wrote:
> Hi, Avadh, > > Thanks for your quick reply. It is really helpful. > > I am wondering what kind of write back policy marss use, write back > allocate or write back non allocate? Since if using write back allocate, > every write miss should incur a load from main memory. I have not figured > it out from marss code. > > It uses write-back allocate method to load the remaining parts of a cache-line from main memory when there is a cache-miss. On a write-miss, it does send the request to lower-cache or RAM to fill in the line. So all the request of type Memory_op_write you see in RAM is caused by a cache-miss and requested a line to fill in from RAM. - Avadh > > Thanks > > Best > zhe > > 2010/11/9 avadh patel <[email protected]> > > On Tue, Nov 9, 2010 at 12:04 PM, zhe <[email protected]> wrote: >> >>> Hi, >>> >>> I do not understand the memory_op_update and memory_op_write >>> operation in the uniprocessor marss write-back configuration. >>> >>> Write-back configured caches uses 'memory_op_update' type of >> configuration >> to perform a 'write-back' when they are evicting a dirty line. >> >> While 'memory_op_write' is mainly used by 'CPU' to generate a write cache >> access. If this misses in caches then it will use same request type to >> load >> data from RAM. >> >> >>> It seems there are both memory_op_update and memory_op_write >>> operation for the main memory access. And it seems there are >>> memory_op_write operation with no data. >>> >>> >> All caches and simulated RAM model doesn't contain any data. Actual data >> is stored in QEMU's emulated RAM model. So none of the simulated cache or >> RAM access contains data. >> >> I am wondering what is the meaning of memory_op_update and >>> memory_op_write operation in the uniprocessor marss write-back >>> configuration? >>> >>> memory_op_write - Generated by CPU for write to a cache line, if it >> misses in >> cache then it sends request to lower level >> caches. >> memory_op_update - Generated by Caches when evicting a dirty line or >> flushing. >> >> - Avadh >> >> Thank you! >>> >>> zhe >>> >>> >>> _______________________________________________ >>> http://www.marss86.org >>> Marss86-Devel mailing list >>> [email protected] >>> https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel >>> >> >> >
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