On Tue, Nov 9, 2010 at 4:09 PM, Ishwar Bhati <[email protected]> wrote: > Dear Avadh, > > I am Ishwar Singh Bhati, PhD student in UMCP. We are integrating the > DiskSim or FlashDim simulator with the MARSS. > > This looks like a very interesting project. Thanks for evaluating our framework for your needs.
I was trying to understand how Hard Disk requests are handled by > PTLsim/QEMU. And at the same time how the time dilation > for the hard disk request is simulated in the PTLSim. Like, how many > simulation cycles PTLSIM will advance, for a Disk data request. > > From my understanding, for a File I/O request, processor will switch to > kernel mode and write in to the dma registers to read/write from the Disk. > And once the > dma has completed the request, it will interrupt the processor that it has > completed the request. And then processor will come back to user mode and > execute the next > instructions. But, how the number of simulation cycles are increasing when > DMA is accessing the IDE disk in the QEMU. > > For this, I am simply copying from my older reply to same question: In QEMU DMA transfers are done in one sim_cycle but the interrupt that generates the DMA completion is delayed by fix value with respect to QEMU's virtual clock. When MARSS is running in simulation mode, QEMU's virtual clock refers to the 'sim_cycle' count of CPU. So if the HDD DMA is using QEMU's virtual clock to generate the interrupt after some specific delay, it will be automatically delayed more in simulation mode according to simulation speed. > Please help me in understanding, how QEMU and PTLSim are interacting for > the Disk requests. And how the clock cycles are advancing. > > You can start looking at some 'ide' device implementation in 'qemu/hw' directory which emulates the ide interface. I am not sure if there is support for SATA or newer interfaces. Thanks, Avadh Thanks > Ishwar >
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