On Mon, Dec 6, 2010 at 10:37 AM, Ishwar Bhati <[email protected]> wrote:
> Thanks Avadh, > > Yes, I observed that ide/dma reads are done in one sim cycle, but their > completion interrupt is happening after a long delay. I am kind of trying > to find out how this delay in interrupt according to virtual clock is > triggered. Where in the code this clock/delay translation is happening, and > this > interrupt is queued.? I suppose, it is happening in QEMU, but I am kind of > not getting the exact place where it is getting done. > > Please, could you point me to a place where this time dilation from real > clock to virtual clock is happening. > > QEMU maintains a virtual clock in 'vl.c' and also provides functions to access virtual clock. Take a look at 'qemu_get_clock' function which uses several low level function to return the clock value. All the IO related function are called from 'qemu_run_timers' (vl.c:4033). All IO emulation logic register timer callback and they are fired at specified time from this location. Try to find how IDE add callback timers to this queue for dma completion. I am still not sure if this is 100% accurate but it might be a good start. You can ask this question on qemu-devel mailing list, someone might have better understanding of your issue. - Avadh > Thanks again. > Ishwar > > On 11/10/2010 2:19 PM, avadh patel wrote: > > > On Tue, Nov 9, 2010 at 4:09 PM, Ishwar Bhati <[email protected]> wrote: > >> Dear Avadh, >> >> I am Ishwar Singh Bhati, PhD student in UMCP. We are integrating the >> DiskSim or FlashDim simulator with the MARSS. >> >> This looks like a very interesting project. Thanks for evaluating our > framework for your needs. > > I was trying to understand how Hard Disk requests are handled by >> PTLsim/QEMU. And at the same time how the time dilation >> for the hard disk request is simulated in the PTLSim. Like, how many >> simulation cycles PTLSIM will advance, for a Disk data request. >> >> From my understanding, for a File I/O request, processor will switch to >> kernel mode and write in to the dma registers to read/write from the Disk. >> And once the >> dma has completed the request, it will interrupt the processor that it has >> completed the request. And then processor will come back to user mode and >> execute the next >> instructions. But, how the number of simulation cycles are increasing when >> DMA is accessing the IDE disk in the QEMU. >> >> For this, I am simply copying from my older reply to same question: > > In QEMU DMA transfers are done in one sim_cycle but the interrupt that > generates the DMA completion is delayed by fix value with respect to QEMU's > virtual clock. When MARSS is running in simulation mode, QEMU's virtual > clock refers to the 'sim_cycle' count of CPU. So if the HDD DMA is using > QEMU's virtual clock to generate the interrupt after some specific delay, it > will be automatically delayed more in simulation mode according to > simulation speed. > > >> Please help me in understanding, how QEMU and PTLSim are interacting for >> the Disk requests. And how the clock cycles are advancing. >> >> You can start looking at some 'ide' device implementation in 'qemu/hw' > directory which emulates the ide interface. I am not sure if there is > support for SATA or newer interfaces. > > Thanks, > Avadh > > Thanks >> Ishwar >> > > >
_______________________________________________ http://www.marss86.org Marss86-Devel mailing list [email protected] https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
