On Mon, May 14, 2012 at 8:46 PM, mihai pricopi <[email protected]>wrote:
> I commented the assert lines for $ and * in the config_gen.py and it > seems it built now. I checked the generated file and looks OK. > I am testing the machine now. > > But the issue is that in auto-generated code, there will be two caches with name L1_I_0 and L1_D_0. This will mess up the stats and other things even if simulation may run without any issue. - Avadh > > On Tue, May 15, 2012 at 11:05 AM, mihai pricopi <[email protected]> > wrote: > > Thanks Avadh, > > > > Is exactly as I tried before, my cache config looks like this: > > > > caches: > > - type: l1_32K_mesi > > name_prefix: L1_I_ > > insts: 6 # Per core L1-I cache > > option: > > private: true > > last_private: true > > - type: l1_32K_mesi > > name_prefix: L1_D_ > > insts: 6 # Per core L1-D cache > > option: > > private: true > > last_private: true > > - type: l1_64K_mesi > > name_prefix: L1_I_ > > insts: 1 # the coalition cache > > option: > > private: true > > last_private: true > > - type: l1_64K_mesi > > name_prefix: L1_D_ > > insts: 1 # the coalition cache > > option: > > private: true > > last_private: true > > - type: l2_256K > > name_prefix: L2_ > > insts: 1 # Shared L2 config > > memory: > > - type: dram_cont > > name_prefix: MEM_ > > insts: 1 # Single DRAM controller > > option: > > latency: 112 > > interconnects: > > - type: p2p > > # '$' sign is used to map matching instances like: > > # cpu_0, L1_I_0 > > connections: > > - core_$: I > > L1_I_$: UPPER > > - core_$: D > > L1_D_$: UPPER > > - L2_0: LOWER > > MEM_0: UPPER > > - type: mesi_bus > > connections: > > - L1_I_*: LOWER > > L1_D_*: LOWER > > L2_0: UPPER > > > > But it doesn't build. This is the build error I get: > > > > Compiling :: ptlsim/build/sim/ptlsim.cpp ==> ptlsim/build/sim/ptlsim.o > > Traceback (most recent call last): > > File "/home/mihai/work/marss/ptlsim/tools/config_gen.py", line 517, > > in <module> > > gen_output_file(config, options) > > File "/home/mihai/work/marss/ptlsim/tools/config_gen.py", line 502, > > in gen_output_file > > generate_machine(config, options) > > File "/home/mihai/work/marss/ptlsim/tools/config_gen.py", line 426, > > in generate_machine > > write_interconn_logic(config, m_conf, of) > > File "/home/mihai/work/marss/ptlsim/tools/config_gen.py", line 337, > > in write_interconn_logic > > assert c_cfg["insts"] == "$NUMCORES" > > AssertionError > > > > Is there any constraint that the $ insts must be equal to NUMCORES ? > > > > Thanks > > > > On Tue, May 15, 2012 at 1:20 AM, avadh patel <[email protected]> > wrote: > >> > >> On Mon, May 14, 2012 at 4:27 AM, mihai pricopi <[email protected] > > > >> wrote: > >>> > >>> Hi, > >>> > >>> I want to build a 7-core machine where 6 cores use l1_32K_ caches and > >>> the 7'th uses a l1_64K cache. I am having difficulties adapting the > >>> config file for this. > >>> Can this be done using the cache section and interconnection ? > >>> > >> It can be done, but its a little tricky configuration. > >> > >> First create machine with min_context and max_context set to 7. > >> Create cores with insts: $NUMCORES > >> > >> In caches, create 6 instances of L1_32K_cache and 1 instance of > >> L1_64K_cache and prefix them with same name 'L1_'. > >> > >> Now when you connect those caches to cores use standard '$' sign > >> to map core-0 to L1_0 and so no. As your L1_64K_cache will be > >> named as L1_6 (it starts with 0), your core-6 will be connected to > >> L1_6. > >> > >> Try this configuration, and to make sure everything is created > >> correctly, check the generated cpp file : > >> 'build/sim/gen_YOUR_MACHINE_NAME.cpp'. > >> > >> > >> - Avadh > >>> > >>> > >>> Thanks > >>> > >>> _______________________________________________ > >>> http://www.marss86.org > >>> Marss86-Devel mailing list > >>> [email protected] > >>> https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > >> > >> >
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