The cache miss latency can be hidden either by this load being done ahead
of time or if there're other instructions that can execute while this load
is outstanding.  So breaking dependency chains is good, but extending the
distance like this seems weird and may hurt common cases.  If ICC does this
type of thing, it'd be interesting to know how it arrives at this decision.

These early loads sound analogous to software prefetch hints, but those are
rife with problems and have very limited application where they win over
hardware.

On Tue, Jan 17, 2017 at 6:58 PM Sergey Melnikov <melnikov.serge...@gmail.com>
wrote:

> In most cases the most heavy instructions are load/stores. So, I believe,
> in this case it's better to try to hide load latency then enable
> macro-fusion. BTW, I'm not sure about SKL/SKX, but for the previous
> generations macro-fusion depends on code alignment.
>
> --Sergey
>
> On Wed, Jan 18, 2017 at 2:44 AM, Aleksey Shipilev <
> aleksey.shipi...@gmail.com> wrote:
>
> (triggered again)
>
>
>
>
>
> On 01/18/2017 12:33 AM, Sergey Melnikov wrote:
>
>
> > mov (%rax), %rbx
>
>
> > cmp %rbx, %rdx
>
>
> > jxx Lxxx
>
>
> >
>
>
> > But if you schedule them this way
>
>
> >
>
>
> > mov (%rax), %rbx
>
>
> > cmp %rbx, %rdx
>
>
> > ... few instructions
>
>
> > jxx Lxxx
>
>
>
>
>
> ...doesn't this give up on macro-fusion, and effectively sets up for a
> better
>
>
> chance of a "bottleneck in instruction fetch/decode phases"? :)
>
>
>
>
>
> -Aleksey
>
>
>
>
>
> --
>
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>
>
> --
>
> --Sergey
>
>
>
>
>
>
>
>
>
>
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