From: Marek Olšák <marek.ol...@amd.com>
This removes s_load_dword latency for tess rings.
We need just 1 SGPR for the address if we use 64K alignment. The final asm
for recreating the descriptor is:
// s2 is (address >> 16)
s_mov_b32 s3, 0
s_lshl_b64 s[4:5], s[2:3], 16
s_mov_b32 s6, -1
s_mov_b32 s7, 0x27fac
---
src/gallium/drivers/radeonsi/si_pm4.h | 2 +-
src/gallium/drivers/radeonsi/si_shader.c | 102 +++++++++++++---------
src/gallium/drivers/radeonsi/si_shader.h | 5 ++
src/gallium/drivers/radeonsi/si_shader_internal.h | 2 +
src/gallium/drivers/radeonsi/si_state.h | 3 -
src/gallium/drivers/radeonsi/si_state_draw.c | 3 +-
src/gallium/drivers/radeonsi/si_state_shaders.c | 50 ++++++++---
7 files changed, 111 insertions(+), 56 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pm4.h
b/src/gallium/drivers/radeonsi/si_pm4.h
index 106abe1..189c481 100644
--- a/src/gallium/drivers/radeonsi/si_pm4.h
+++ b/src/gallium/drivers/radeonsi/si_pm4.h
@@ -23,21 +23,21 @@
* Authors:
* Christian König <christian.koe...@amd.com>
*/
#ifndef SI_PM4_H
#define SI_PM4_H
#include "radeon/radeon_winsys.h"
#define SI_PM4_MAX_DW 176
-#define SI_PM4_MAX_BO 1
+#define SI_PM4_MAX_BO 3
// forward defines
struct si_context;
enum chip_class;
struct si_pm4_state
{
/* optional indirect buffer */
struct r600_resource *indirect_buffer;
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 974be02..57bcd6b 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -904,20 +904,43 @@ static void lds_store(struct lp_build_tgsi_context
*bld_base,
struct gallivm_state *gallivm = &ctx->gallivm;
dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
LLVMConstInt(ctx->i32, dw_offset_imm, 0));
value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
ac_build_indexed_store(&ctx->ac, ctx->lds,
dw_addr, value);
}
+static LLVMValueRef desc_from_addr_base64k(struct si_shader_context *ctx,
+ unsigned param)
+{
+ LLVMBuilderRef builder = ctx->gallivm.builder;
+
+ LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
+ addr = LLVMBuildZExt(builder, addr, ctx->i64, "");
+ addr = LLVMBuildShl(builder, addr, LLVMConstInt(ctx->i64, 16, 0), "");
+
+ uint64_t desc2 = 0xffffffff;
+ uint64_t desc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
+ S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
+ S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
+ S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
+ S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+ S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+ LLVMValueRef hi = LLVMConstInt(ctx->i64, desc2 | (desc3 << 32), 0);
+
+ LLVMValueRef desc = LLVMGetUndef(LLVMVectorType(ctx->i64, 2));
+ desc = LLVMBuildInsertElement(builder, desc, addr, ctx->i32_0, "");
+ return LLVMBuildInsertElement(builder, desc, hi, ctx->i32_1, "");
+}
+
static LLVMValueRef fetch_input_tcs(
struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_src_register *reg,
enum tgsi_opcode_type type, unsigned swizzle)
{
struct si_shader_context *ctx = si_shader_context(bld_base);
LLVMValueRef dw_addr, stride;
stride = unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
dw_addr = get_tcs_in_current_patch_offset(ctx);
@@ -945,45 +968,42 @@ static LLVMValueRef fetch_output_tcs(
return lds_load(bld_base, type, swizzle, dw_addr);
}
static LLVMValueRef fetch_input_tes(
struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_src_register *reg,
enum tgsi_opcode_type type, unsigned swizzle)
{
struct si_shader_context *ctx = si_shader_context(bld_base);
- LLVMValueRef rw_buffers, buffer, base, addr;
+ LLVMValueRef buffer, base, addr;
- rw_buffers = LLVMGetParam(ctx->main_fn,
- ctx->param_rw_buffers);
- buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
- LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
+ buffer = desc_from_addr_base64k(ctx,
ctx->param_tcs_offchip_addr_base64k);
base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
return buffer_load(bld_base, type, swizzle, buffer, base, addr, true);
}
static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_instruction *inst,
const struct tgsi_opcode_info *info,
LLVMValueRef dst[4])
{
struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = &ctx->gallivm;
const struct tgsi_full_dst_register *reg = &inst->Dst[0];
const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
unsigned chan_index;
LLVMValueRef dw_addr, stride;
- LLVMValueRef rw_buffers, buffer, base, buf_addr;
+ LLVMValueRef buffer, base, buf_addr;
LLVMValueRef values[4];
bool skip_lds_store;
bool is_tess_factor = false;
/* Only handle per-patch and per-vertex outputs here.
* Vectors will be lowered to scalars and this function will be called
again.
*/
if (reg->Register.File != TGSI_FILE_OUTPUT ||
(dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) ==
LLVMVectorTypeKind)) {
si_llvm_emit_store(bld_base, inst, info, dst);
@@ -1005,24 +1025,21 @@ static void store_output_tcs(struct
lp_build_tgsi_context *bld_base,
/* Always write tess factors into LDS for the TCS
epilog. */
if (name == TGSI_SEMANTIC_TESSINNER ||
name == TGSI_SEMANTIC_TESSOUTER) {
skip_lds_store = false;
is_tess_factor = true;
}
}
}
- rw_buffers = LLVMGetParam(ctx->main_fn,
- ctx->param_rw_buffers);
- buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
- LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
+ buffer = desc_from_addr_base64k(ctx,
ctx->param_tcs_offchip_addr_base64k);
base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
LLVMValueRef value = dst[chan_index];
if (inst->Instruction.Saturate)
value = ac_build_clamp(&ctx->ac, value);
@@ -1528,27 +1545,24 @@ static void declare_system_value(struct
si_shader_context *ctx,
value = unpack_param(ctx,
ctx->param_tcs_out_lds_layout, 26, 6);
else if (ctx->type == PIPE_SHADER_TESS_EVAL)
value = unpack_param(ctx,
ctx->param_tcs_offchip_layout, 9, 7);
else
assert(!"invalid shader stage for
TGSI_SEMANTIC_VERTICESIN");
break;
case TGSI_SEMANTIC_TESSINNER:
case TGSI_SEMANTIC_TESSOUTER:
{
- LLVMValueRef rw_buffers, buffer, base, addr;
+ LLVMValueRef buffer, base, addr;
int param = si_shader_io_get_unique_index(decl->Semantic.Name,
0);
- rw_buffers = LLVMGetParam(ctx->main_fn,
- ctx->param_rw_buffers);
- buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
- LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
+ buffer = desc_from_addr_base64k(ctx,
ctx->param_tcs_offchip_addr_base64k);
base = LLVMGetParam(ctx->main_fn,
ctx->param_tcs_offchip_offset);
addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
NULL,
LLVMConstInt(ctx->i32, param, 0));
value = buffer_load(&ctx->bld_base, TGSI_TYPE_FLOAT,
~0, buffer, base, addr, true);
break;
}
@@ -2424,30 +2438,26 @@ handle_semantic:
}
/**
* Forward all outputs from the vertex shader to the TES. This is only used
* for the fixed function TCS.
*/
static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
{
struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = &ctx->gallivm;
- LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
+ LLVMValueRef invocation_id, buffer, buffer_offset;
LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
uint64_t inputs;
invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
-
- rw_buffers = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
- buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
- LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
-
+ buffer = desc_from_addr_base64k(ctx,
ctx->param_tcs_offchip_addr_base64k);
buffer_offset = LLVMGetParam(ctx->main_fn,
ctx->param_tcs_offchip_offset);
lds_vertex_stride = unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
lds_vertex_stride, "");
lds_base = get_tcs_in_current_patch_offset(ctx);
lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset,
"");
inputs = ctx->shader->key.mono.ff_tcs_inputs_to_copy;
while (inputs) {
@@ -2473,21 +2483,21 @@ static void si_copy_tcs_inputs(struct
lp_build_tgsi_context *bld_base)
static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
LLVMValueRef rel_patch_id,
LLVMValueRef invocation_id,
LLVMValueRef
tcs_out_current_patch_data_offset)
{
struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = &ctx->gallivm;
struct si_shader *shader = ctx->shader;
unsigned tess_inner_index, tess_outer_index;
LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
- LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base, inner[4],
outer[4];
+ LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
unsigned stride, outer_comps, inner_comps, i, offset;
struct lp_build_if_state if_ctx, inner_if_ctx;
si_llvm_emit_barrier(NULL, bld_base, NULL);
/* Do this only for invocation 0, because the tess levels are per-patch,
* not per-vertex.
*
* This can't jump, because invocation 0 executes this. It should
* at least mask out the loads and stores for other invocations.
@@ -2555,24 +2565,21 @@ static void si_write_tess_factors(struct
lp_build_tgsi_context *bld_base,
}
/* Convert the outputs to vectors for stores. */
vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
vec1 = NULL;
if (stride > 4)
vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
/* Get the buffer. */
- rw_buffers = LLVMGetParam(ctx->main_fn,
- ctx->param_rw_buffers);
- buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
- LLVMConstInt(ctx->i32, SI_HS_RING_TESS_FACTOR, 0));
+ buffer = desc_from_addr_base64k(ctx,
ctx->param_tcs_factor_addr_base64k);
/* Get the offset. */
tf_base = LLVMGetParam(ctx->main_fn,
ctx->param_tcs_factor_offset);
byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
LLVMConstInt(ctx->i32, 4 * stride, 0), "");
lp_build_if(&inner_if_ctx, gallivm,
LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
rel_patch_id, ctx->i32_0, ""));
@@ -2598,22 +2605,21 @@ static void si_write_tess_factors(struct
lp_build_tgsi_context *bld_base,
ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
stride - 4, byteoffset, tf_base,
offset, 1, 0, true, false);
/* Store the tess factors into the offchip buffer if TES reads them. */
if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
LLVMValueRef tf_inner_offset;
unsigned param_outer, param_inner;
- buf = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
- LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP,
0));
+ buf = desc_from_addr_base64k(ctx,
ctx->param_tcs_offchip_addr_base64k);
base = LLVMGetParam(ctx->main_fn,
ctx->param_tcs_offchip_offset);
param_outer = si_shader_io_get_unique_index(
TGSI_SEMANTIC_TESSOUTER, 0);
tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id,
NULL,
LLVMConstInt(ctx->i32, param_outer, 0));
outer_vec = lp_build_gather_values(gallivm, outer,
util_next_power_of_two(outer_comps));
@@ -2684,33 +2690,38 @@ static void si_llvm_emit_tcs_epilogue(struct
lp_build_tgsi_context *bld_base)
rel_patch_id = get_rel_patch_id(ctx);
invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
/* Return epilog parameters from this function. */
LLVMBuilderRef builder = ctx->gallivm.builder;
LLVMValueRef ret = ctx->return_value;
unsigned vgpr;
- ret = si_insert_input_ptr_as_2xi32(ctx, ret,
- ctx->param_rw_buffers, 0);
-
if (ctx->screen->b.chip_class >= GFX9) {
ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_offchip_layout,
8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
+ ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_offchip_addr_base64k,
+ 8 +
GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
+ ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_factor_addr_base64k,
+ 8 +
GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
/* Tess offchip and tess factor offsets are at the beginning. */
ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_offchip_offset, 2);
ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_factor_offset, 4);
- vgpr = 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT + 1;
+ vgpr = 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K + 1;
} else {
ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_offchip_layout,
GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
+ ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_offchip_addr_base64k,
+ GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
+ ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_factor_addr_base64k,
+ GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K);
/* Tess offchip and tess factor offsets are after user SGPRs. */
ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_offchip_offset,
GFX6_TCS_NUM_USER_SGPR);
ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_factor_offset,
GFX6_TCS_NUM_USER_SGPR + 1);
vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
}
/* VGPRs */
rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
@@ -2735,22 +2746,26 @@ static void si_set_ls_return_value_for_tcs(struct
si_shader_context *ctx)
ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset,
5);
ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
8 + SI_SGPR_VS_STATE_BITS);
ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
8 + GFX9_SGPR_TCS_OUT_OFFSETS);
ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
8 + GFX9_SGPR_TCS_OUT_LAYOUT);
+ ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
+ 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
+ ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
+ 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
- unsigned desc_param = ctx->param_tcs_out_lds_layout + 2;
+ unsigned desc_param = ctx->param_tcs_factor_addr_base64k + 2;
ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
8 + GFX9_SGPR_TCS_CONST_BUFFERS);
ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
8 + GFX9_SGPR_TCS_SAMPLERS);
ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 2,
8 + GFX9_SGPR_TCS_IMAGES);
ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 3,
8 + GFX9_SGPR_TCS_SHADER_BUFFERS);
unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
@@ -5914,20 +5929,22 @@ static void create_function(struct si_shader_context
*ctx)
declare_vs_input_vgprs(ctx, params, &num_params,
&num_prolog_vgprs);
break;
case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
declare_default_desc_pointers(ctx, params, &num_params);
params[ctx->param_tcs_offchip_layout = num_params++] = ctx->i32;
params[ctx->param_tcs_out_lds_offsets = num_params++] =
ctx->i32;
params[ctx->param_tcs_out_lds_layout = num_params++] = ctx->i32;
params[ctx->param_vs_state_bits = num_params++] = ctx->i32;
+ params[ctx->param_tcs_offchip_addr_base64k = num_params++] =
ctx->i32;
+ params[ctx->param_tcs_factor_addr_base64k = num_params++] =
ctx->i32;
params[ctx->param_tcs_offchip_offset = num_params++] = ctx->i32;
params[ctx->param_tcs_factor_offset = num_params++] = ctx->i32;
last_sgpr = num_params - 1;
/* VGPRs */
params[ctx->param_tcs_patch_id = num_params++] = ctx->i32;
params[ctx->param_tcs_rel_ids = num_params++] = ctx->i32;
/* param_tcs_offchip_offset and param_tcs_factor_offset are
* placed after the user SGPRs.
@@ -5951,20 +5968,22 @@ static void create_function(struct si_shader_context
*ctx)
params[num_params++] = ctx->i32; /* unused */
params[num_params++] = ctx->i32; /* unused */
declare_per_stage_desc_pointers(ctx, params, &num_params,
ctx->type ==
PIPE_SHADER_VERTEX);
declare_vs_specific_input_sgprs(ctx, params, &num_params);
params[ctx->param_tcs_offchip_layout = num_params++] = ctx->i32;
params[ctx->param_tcs_out_lds_offsets = num_params++] =
ctx->i32;
params[ctx->param_tcs_out_lds_layout = num_params++] = ctx->i32;
+ params[ctx->param_tcs_offchip_addr_base64k = num_params++] =
ctx->i32;
+ params[ctx->param_tcs_factor_addr_base64k = num_params++] =
ctx->i32;
params[num_params++] = ctx->i32; /* unused */
declare_per_stage_desc_pointers(ctx, params, &num_params,
ctx->type ==
PIPE_SHADER_TESS_CTRL);
last_sgpr = num_params - 1;
/* VGPRs (first TCS, then VS) */
params[ctx->param_tcs_patch_id = num_params++] = ctx->i32;
params[ctx->param_tcs_rel_ids = num_params++] = ctx->i32;
@@ -5977,21 +5996,21 @@ static void create_function(struct si_shader_context
*ctx)
returns[num_returns++] = ctx->i32; /* SGPRs */
for (i = 0; i < 2; i++)
returns[num_returns++] = ctx->f32; /* VGPRs */
} else {
/* TCS return values are inputs to the TCS epilog.
*
* param_tcs_offchip_offset, param_tcs_factor_offset,
* param_tcs_offchip_layout, and param_rw_buffers
* should be passed to the epilog.
*/
- for (i = 0; i <= 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT; i++)
+ for (i = 0; i <= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K;
i++)
returns[num_returns++] = ctx->i32; /* SGPRs */
for (i = 0; i < 3; i++)
returns[num_returns++] = ctx->f32; /* VGPRs */
}
break;
case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
/* Merged stages have 8 system SGPRs at the beginning. */
params[ctx->param_rw_buffers = num_params++] = /*
SPI_SHADER_USER_DATA_ADDR_LO_GS */
const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
@@ -6006,21 +6025,21 @@ static void create_function(struct si_shader_context
*ctx)
params[num_params++] = ctx->i32; /* unused */
declare_per_stage_desc_pointers(ctx, params, &num_params,
(ctx->type ==
PIPE_SHADER_VERTEX ||
ctx->type ==
PIPE_SHADER_TESS_EVAL));
if (ctx->type == PIPE_SHADER_VERTEX) {
declare_vs_specific_input_sgprs(ctx, params,
&num_params);
} else {
/* TESS_EVAL (and also GEOMETRY):
* Declare as many input SGPRs as the VS has. */
params[ctx->param_tcs_offchip_layout = num_params++] =
ctx->i32;
- params[num_params++] = ctx->i32; /* unused */
+ params[ctx->param_tcs_offchip_addr_base64k =
num_params++] = ctx->i32;
params[num_params++] = ctx->i32; /* unused */
params[num_params++] = ctx->i32; /* unused */
params[num_params++] = ctx->i32; /* unused */
params[ctx->param_vs_state_bits = num_params++] =
ctx->i32; /* unused */
}
declare_per_stage_desc_pointers(ctx, params, &num_params,
ctx->type ==
PIPE_SHADER_GEOMETRY);
last_sgpr = num_params - 1;
@@ -6044,20 +6063,21 @@ static void create_function(struct si_shader_context
*ctx)
for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
returns[num_returns++] = ctx->i32; /* SGPRs */
for (i = 0; i < 5; i++)
returns[num_returns++] = ctx->f32; /* VGPRs */
}
break;
case PIPE_SHADER_TESS_EVAL:
declare_default_desc_pointers(ctx, params, &num_params);
params[ctx->param_tcs_offchip_layout = num_params++] = ctx->i32;
+ params[ctx->param_tcs_offchip_addr_base64k = num_params++] =
ctx->i32;
if (shader->key.as_es) {
params[ctx->param_tcs_offchip_offset = num_params++] =
ctx->i32;
params[num_params++] = ctx->i32;
params[ctx->param_es2gs_offset = num_params++] =
ctx->i32;
} else {
params[num_params++] = ctx->i32;
declare_streamout_params(ctx, &shader->selector->so,
params, ctx->i32, &num_params);
params[ctx->param_tcs_offchip_offset = num_params++] =
ctx->i32;
@@ -8578,51 +8598,55 @@ static bool si_shader_select_vs_parts(struct si_screen
*sscreen,
*/
static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
union si_shader_part_key *key)
{
struct gallivm_state *gallivm = &ctx->gallivm;
struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
LLVMTypeRef params[32];
LLVMValueRef func;
int last_sgpr, num_params = 0;
- /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
- params[ctx->param_rw_buffers = num_params++] =
- const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
-
if (ctx->screen->b.chip_class >= GFX9) {
+ params[num_params++] = ctx->i64;
params[ctx->param_tcs_offchip_offset = num_params++] = ctx->i32;
params[num_params++] = ctx->i32; /* wave info */
params[ctx->param_tcs_factor_offset = num_params++] = ctx->i32;
params[num_params++] = ctx->i32;
params[num_params++] = ctx->i32;
params[num_params++] = ctx->i32;
params[num_params++] = ctx->i64;
params[num_params++] = ctx->i64;
params[num_params++] = ctx->i64;
params[num_params++] = ctx->i64;
params[num_params++] = ctx->i64;
params[num_params++] = ctx->i64;
params[num_params++] = ctx->i32;
params[num_params++] = ctx->i32;
params[num_params++] = ctx->i32;
params[num_params++] = ctx->i32;
params[ctx->param_tcs_offchip_layout = num_params++] = ctx->i32;
+ params[num_params++] = ctx->i32;
+ params[num_params++] = ctx->i32;
+ params[ctx->param_tcs_offchip_addr_base64k = num_params++] =
ctx->i32;
+ params[ctx->param_tcs_factor_addr_base64k = num_params++] =
ctx->i32;
} else {
params[num_params++] = ctx->i64;
params[num_params++] = ctx->i64;
params[num_params++] = ctx->i64;
params[num_params++] = ctx->i64;
+ params[num_params++] = ctx->i64;
params[ctx->param_tcs_offchip_layout = num_params++] = ctx->i32;
params[num_params++] = ctx->i32;
params[num_params++] = ctx->i32;
params[num_params++] = ctx->i32;
+ params[ctx->param_tcs_offchip_addr_base64k = num_params++] =
ctx->i32;
+ params[ctx->param_tcs_factor_addr_base64k = num_params++] =
ctx->i32;
params[ctx->param_tcs_offchip_offset = num_params++] = ctx->i32;
params[ctx->param_tcs_factor_offset = num_params++] = ctx->i32;
}
last_sgpr = num_params - 1;
params[num_params++] = ctx->i32; /* patch index within the wave
(REL_PATCH_ID) */
params[num_params++] = ctx->i32; /* invocation ID within the patch */
params[num_params++] = ctx->i32; /* LDS offset where tess factors
should be loaded from */
/* Create the function. */
diff --git a/src/gallium/drivers/radeonsi/si_shader.h
b/src/gallium/drivers/radeonsi/si_shader.h
index d051715..c9bd904 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -166,33 +166,38 @@ enum {
SI_SGPR_VERTEX_BUFFERS = SI_NUM_RESOURCE_SGPRS,
SI_SGPR_VERTEX_BUFFERS_HI,
SI_SGPR_BASE_VERTEX,
SI_SGPR_START_INSTANCE,
SI_SGPR_DRAWID,
SI_SGPR_VS_STATE_BITS,
SI_VS_NUM_USER_SGPR,
/* TES */
SI_SGPR_TES_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
+ SI_SGPR_TES_OFFCHIP_ADDR_BASE64K,
SI_TES_NUM_USER_SGPR,
/* GFX6-8: TCS only */
GFX6_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
GFX6_SGPR_TCS_OUT_OFFSETS,
GFX6_SGPR_TCS_OUT_LAYOUT,
GFX6_SGPR_TCS_IN_LAYOUT,
+ GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K,
+ GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K,
GFX6_TCS_NUM_USER_SGPR,
/* GFX9: Merged LS-HS (VS-TCS) only. */
GFX9_SGPR_TCS_OFFCHIP_LAYOUT = SI_VS_NUM_USER_SGPR,
GFX9_SGPR_TCS_OUT_OFFSETS,
GFX9_SGPR_TCS_OUT_LAYOUT,
+ GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K,
+ GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K,
GFX9_SGPR_unused_to_align_the_next_pointer,
GFX9_SGPR_TCS_CONST_BUFFERS,
GFX9_SGPR_TCS_CONST_BUFFERS_HI,
GFX9_SGPR_TCS_SAMPLERS, /* images & sampler states interleaved */
GFX9_SGPR_TCS_SAMPLERS_HI,
GFX9_SGPR_TCS_IMAGES,
GFX9_SGPR_TCS_IMAGES_HI,
GFX9_SGPR_TCS_SHADER_BUFFERS,
GFX9_SGPR_TCS_SHADER_BUFFERS_HI,
GFX9_TCS_NUM_USER_SGPR,
diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h
b/src/gallium/drivers/radeonsi/si_shader_internal.h
index 233a96f..8a9bf10 100644
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -155,20 +155,22 @@ struct si_shader_context {
*/
int param_tcs_out_lds_offsets;
/* Layout of TCS outputs / TES inputs:
* [0:12] = stride between output patches in DW, num_outputs *
num_vertices * 4
* max = 32*32*4
* [13:20] = stride between output vertices in DW = num_inputs * 4
* max = 32*4
* [26:31] = gl_PatchVerticesIn, max = 32
*/
int param_tcs_out_lds_layout;
+ int param_tcs_offchip_addr_base64k;
+ int param_tcs_factor_addr_base64k;
int param_tcs_offchip_offset;
int param_tcs_factor_offset;
int param_tcs_patch_id;
int param_tcs_rel_ids;
/* API TES */
int param_tes_u;
int param_tes_v;
int param_tes_rel_patch_id;
int param_tes_patch_id;
diff --git a/src/gallium/drivers/radeonsi/si_state.h
b/src/gallium/drivers/radeonsi/si_state.h
index 6257299..629d614 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -157,23 +157,20 @@ union si_state_atoms {
#define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
struct si_shader_data {
struct r600_atom atom;
uint32_t sh_base[SI_NUM_SHADERS];
};
/* Private read-write buffer slots. */
enum {
- SI_HS_RING_TESS_FACTOR,
- SI_HS_RING_TESS_OFFCHIP,
-
SI_ES_RING_ESGS,
SI_GS_RING_ESGS,
SI_RING_GSVS,
SI_VS_STREAMOUT_BUF0,
SI_VS_STREAMOUT_BUF1,
SI_VS_STREAMOUT_BUF2,
SI_VS_STREAMOUT_BUF3,
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 393f64f..6a756c4 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -260,22 +260,23 @@ static void si_emit_derived_tess_state(struct si_context
*sctx,
/* Set userdata SGPRs for TCS. */
radeon_set_sh_reg_seq(cs,
R_00B430_SPI_SHADER_USER_DATA_HS_0 +
GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
radeon_emit(cs, offchip_layout);
radeon_emit(cs, tcs_out_offsets);
radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
radeon_emit(cs, tcs_in_layout);
}
/* Set userdata SGPRs for TES. */
- radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4,
1);
+ radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4,
2);
radeon_emit(cs, offchip_layout);
+ radeon_emit(cs, r600_resource(sctx->tess_offchip_ring)->gpu_address >>
16);
ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
if (sctx->b.chip_class >= CIK)
radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
ls_hs_config);
else
radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index f9cd5c3..278766f 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2758,80 +2758,106 @@ static void si_init_tess_factor_ring(struct si_context
*sctx)
case VI:
case GFX9:
max_offchip_buffers = MIN2(max_offchip_buffers, 508);
break;
default:
assert(0);
return;
}
assert(!sctx->tf_ring);
+ /* Use 64K alignment for both rings, so that we can pass the address
+ * to shaders as one SGPR containing bits [16:47].
+ */
sctx->tf_ring = r600_aligned_buffer_create(sctx->b.b.screen,
R600_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
32768 *
sctx->screen->b.info.max_se,
- 256);
+ 64 * 1024);
if (!sctx->tf_ring)
return;
assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
sctx->tess_offchip_ring =
r600_aligned_buffer_create(sctx->b.b.screen,
R600_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
max_offchip_buffers *
sctx->screen->tess_offchip_block_dw_size * 4,
- 256);
+ 64 * 1024);
if (!sctx->tess_offchip_ring)
return;
si_init_config_add_vgt_flush(sctx);
+ uint64_t offchip_va =
r600_resource(sctx->tess_offchip_ring)->gpu_address;
+ uint64_t factor_va = r600_resource(sctx->tf_ring)->gpu_address;
+ assert((offchip_va & 0xffff) == 0);
+ assert((factor_va & 0xffff) == 0);
+
+ si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_offchip_ring),
+ RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
+ si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tf_ring),
+ RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
+
/* Append these registers to the init config state. */
if (sctx->b.chip_class >= CIK) {
if (sctx->b.chip_class >= VI)
--max_offchip_buffers;
si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
S_030938_SIZE(sctx->tf_ring->width0 / 4));
si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
- r600_resource(sctx->tf_ring)->gpu_address >> 8);
+ factor_va >> 8);
if (sctx->b.chip_class >= GFX9)
si_pm4_set_reg(sctx->init_config,
R_030944_VGT_TF_MEMORY_BASE_HI,
-
r600_resource(sctx->tf_ring)->gpu_address >> 40);
+ factor_va >> 40);
si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
} else {
assert(offchip_granularity == V_03093C_X_8K_DWORDS);
si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
S_008988_SIZE(sctx->tf_ring->width0 / 4));
si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
- r600_resource(sctx->tf_ring)->gpu_address >> 8);
+ factor_va >> 8);
si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
}
+ if (sctx->b.chip_class >= GFX9) {
+ si_pm4_set_reg(sctx->init_config,
+ R_00B430_SPI_SHADER_USER_DATA_LS_0 +
+ GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
+ offchip_va >> 16);
+ si_pm4_set_reg(sctx->init_config,
+ R_00B430_SPI_SHADER_USER_DATA_LS_0 +
+ GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
+ factor_va >> 16);
+ } else {
+ si_pm4_set_reg(sctx->init_config,
+ R_00B430_SPI_SHADER_USER_DATA_HS_0 +
+ GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
+ offchip_va >> 16);
+ si_pm4_set_reg(sctx->init_config,
+ R_00B430_SPI_SHADER_USER_DATA_HS_0 +
+ GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
+ factor_va >> 16);
+ }
+
/* Flush the context to re-emit the init_config state.
* This is done only once in a lifetime of a context.
*/
si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
sctx->b.initial_gfx_cs_size = 0; /* force flush */
si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
-
- si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
- 0, sctx->tf_ring->width0, false, false, 0, 0, 0);
-
- si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_OFFCHIP,
- sctx->tess_offchip_ring, 0,
- sctx->tess_offchip_ring->width0, false, false, 0, 0,
0);
}
/**
* This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
* VS passes its outputs to TES directly, so the fixed-function shader only
* has to write TESSOUTER and TESSINNER.
*/
static void si_generate_fixed_func_tcs(struct si_context *sctx)
{
struct ureg_src outer, inner;
--
2.7.4
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