On 16.06.2017 14:58, Marek Olšák wrote:
From: Marek Olšák <marek.ol...@amd.com>
The kernel sort of does the same thing with fences.
The kernel sends an EVENT_WRITE_EOP with various TC flags. Is that
guaranteed to wait for shaders to finish and flush their data? I'm
mostly thinking about synchronizing with CPU reads here.
While reading, I noticed that si_emit_cache_flush has a path where L1 is
invalidated _after_ L2 writeback. What's up with that? Couldn't it
happen that there's data in L1 which is not yet written to L2? Seems odd.
Cheers,
Nicolai
---
src/gallium/drivers/radeonsi/si_hw_context.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c
b/src/gallium/drivers/radeonsi/si_hw_context.c
index 345825a..5d930a6 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -122,27 +122,27 @@ void si_context_gfx_flush(void *context, unsigned flags,
}
ctx->gfx_flush_in_progress = true;
/* This CE dump should be done in parallel with the last draw. */
if (ctx->ce_ib)
si_ce_save_all_descriptors_at_ib_end(ctx);
r600_preflush_suspend_features(&ctx->b);
- ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
- SI_CONTEXT_PS_PARTIAL_FLUSH;
-
/* DRM 3.1.0 doesn't flush TC for VI correctly. */
- if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1)
- ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 |
+ if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1) {
+ ctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
+ SI_CONTEXT_CS_PARTIAL_FLUSH |
+ SI_CONTEXT_INV_GLOBAL_L2 |
SI_CONTEXT_INV_VMEM_L1;
+ }
si_emit_cache_flush(ctx);
if (ctx->trace_buf)
si_trace_emit(ctx);
if (ctx->is_debug) {
/* Save the IB for debug contexts. */
radeon_clear_saved_cs(&ctx->last_gfx);
radeon_save_cs(ws, cs, &ctx->last_gfx);
--
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.
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