---
src/compiler/nir/nir_builder_opcodes_h.py | 44 ++++++++++++++++++++++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir_builder_opcodes_h.py
b/src/compiler/nir/nir_builder_opcodes_h.py
index e600093e9f6..a9de0e4ea47 100644
--- a/src/compiler/nir/nir_builder_opcodes_h.py
+++ b/src/compiler/nir/nir_builder_opcodes_h.py
@@ -27,6 +27,41 @@ template = """\
#define _NIR_BUILDER_OPCODES_
<%
+opcode_remap = {
+ 'b2i' : 'b322i',
+ 'b2f' : 'b322f',
+ 'i2b' : 'i2b32',
+ 'f2b' : 'f2b32',
+
+ 'flt' : 'flt32',
+ 'fge' : 'fge32',
+ 'feq' : 'feq32',
+ 'fne' : 'fne32',
+ 'ilt' : 'ilt32',
+ 'ige' : 'ige32',
+ 'ieq' : 'ieq32',
+ 'ine' : 'ine32',
+ 'ult' : 'ult32',
+ 'uge' : 'uge32',
+
+ 'ball_iequal2' : 'b32all_iequal2',
+ 'ball_iequal3' : 'b32all_iequal3',
+ 'ball_iequal4' : 'b32all_iequal4',
+ 'bany_inequal2' : 'b32any_inequal2',
+ 'bany_inequal3' : 'b32any_inequal3',
+ 'bany_inequal4' : 'b32any_inequal4',
+ 'ball_fequal2' : 'b32all_fequal2',
+ 'ball_fequal3' : 'b32all_fequal3',
+ 'ball_fequal4' : 'b32all_fequal4',
+ 'bany_fnequal2' : 'b32any_fnequal2',
+ 'bany_fnequal3' : 'b32any_fnequal3',
+ 'bany_fnequal4' : 'b32any_fnequal4',
+
+ 'bcsel' : 'b32csel',
+}
+
+opcode_remap32 = { op32 : op for op, op32 in opcode_remap.items() }
+
def src_decl_list(num_srcs):
return ', '.join('nir_ssa_def *src' + str(i) for i in range(num_srcs))
@@ -35,8 +70,15 @@ def src_list(num_srcs):
%>
% for name, opcode in sorted(opcodes.items()):
+ % if name in opcode_remap:
+ <% continue %>
+ % elif name in opcode_remap32:
+ <% builder_name = opcode_remap32[name] %>
+ % else:
+ <% builder_name = name %>
+ % endif
static inline nir_ssa_def *
-nir_${name}(nir_builder *build, ${src_decl_list(opcode.num_inputs)})
+nir_${builder_name}(nir_builder *build, ${src_decl_list(opcode.num_inputs)})
{
return nir_build_alu(build, nir_op_${name}, ${src_list(opcode.num_inputs)});
}
--
2.19.1
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