Generated with a little hand-editing and the following sed commands: sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c --- src/compiler/nir/nir.h | 24 ++++----- src/compiler/nir/nir_loop_analyze.c | 28 +++++----- src/compiler/nir/nir_opt_if.c | 2 +- src/compiler/nir/nir_opt_peephole_select.c | 2 +- src/compiler/nir/nir_opt_undef.c | 2 +- src/compiler/spirv/vtn_alu.c | 62 +++++++++++----------- 6 files changed, 60 insertions(+), 60 deletions(-)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 93d0fb5271c..47c7f400b2d 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -1504,18 +1504,18 @@ static inline bool nir_alu_instr_is_comparison(const nir_alu_instr *instr) { switch (instr->op) { - case nir_op_flt: - case nir_op_fge: - case nir_op_feq: - case nir_op_fne: - case nir_op_ilt: - case nir_op_ult: - case nir_op_ige: - case nir_op_uge: - case nir_op_ieq: - case nir_op_ine: - case nir_op_i2b: - case nir_op_f2b: + case nir_op_flt32: + case nir_op_fge32: + case nir_op_feq32: + case nir_op_fne32: + case nir_op_ilt32: + case nir_op_ult32: + case nir_op_ige32: + case nir_op_uge32: + case nir_op_ieq32: + case nir_op_ine32: + case nir_op_i2b32: + case nir_op_f2b32: case nir_op_inot: case nir_op_fnot: return true; diff --git a/src/compiler/nir/nir_loop_analyze.c b/src/compiler/nir/nir_loop_analyze.c index 9c3fd2f286f..37409525bbb 100644 --- a/src/compiler/nir/nir_loop_analyze.c +++ b/src/compiler/nir/nir_loop_analyze.c @@ -357,26 +357,26 @@ get_iteration(nir_op cond_op, nir_const_value *initial, nir_const_value *step, int32_t iter; switch (cond_op) { - case nir_op_ige: - case nir_op_ilt: - case nir_op_ieq: - case nir_op_ine: { + case nir_op_ige32: + case nir_op_ilt32: + case nir_op_ieq32: + case nir_op_ine32: { int32_t initial_val = initial->i32[0]; int32_t span = limit->i32[0] - initial_val; iter = span / step->i32[0]; break; } - case nir_op_uge: - case nir_op_ult: { + case nir_op_uge32: + case nir_op_ult32: { uint32_t initial_val = initial->u32[0]; uint32_t span = limit->u32[0] - initial_val; iter = span / step->u32[0]; break; } - case nir_op_fge: - case nir_op_flt: - case nir_op_feq: - case nir_op_fne: { + case nir_op_fge32: + case nir_op_flt32: + case nir_op_feq32: + case nir_op_fne32: { float initial_val = initial->f32[0]; float span = limit->f32[0] - initial_val; iter = span / step->f32[0]; @@ -547,10 +547,10 @@ find_trip_count(loop_info_state *state) bool limit_rhs = true; switch (alu->op) { - case nir_op_fge: case nir_op_ige: case nir_op_uge: - case nir_op_flt: case nir_op_ilt: case nir_op_ult: - case nir_op_feq: case nir_op_ieq: - case nir_op_fne: case nir_op_ine: + case nir_op_fge32: case nir_op_ige32: case nir_op_uge32: + case nir_op_flt32: case nir_op_ilt32: case nir_op_ult32: + case nir_op_feq32: case nir_op_ieq32: + case nir_op_fne32: case nir_op_ine32: /* We assume that the limit is the "right" operand */ basic_ind = get_loop_var(alu->src[0].src.ssa, state); diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c index 60368a0259e..cdad06c1c48 100644 --- a/src/compiler/nir/nir_opt_if.c +++ b/src/compiler/nir/nir_opt_if.c @@ -478,7 +478,7 @@ can_propagate_through_alu(nir_src *src) (nir_instr_as_alu(src->parent_instr)->op == nir_op_ior || nir_instr_as_alu(src->parent_instr)->op == nir_op_iand || nir_instr_as_alu(src->parent_instr)->op == nir_op_inot || - nir_instr_as_alu(src->parent_instr)->op == nir_op_b2i)) + nir_instr_as_alu(src->parent_instr)->op == nir_op_b322i)) return true; return false; diff --git a/src/compiler/nir/nir_opt_peephole_select.c b/src/compiler/nir/nir_opt_peephole_select.c index ad9d0abec03..6308c8cab12 100644 --- a/src/compiler/nir/nir_opt_peephole_select.c +++ b/src/compiler/nir/nir_opt_peephole_select.c @@ -205,7 +205,7 @@ nir_opt_peephole_select_block(nir_block *block, nir_shader *shader, break; nir_phi_instr *phi = nir_instr_as_phi(instr); - nir_alu_instr *sel = nir_alu_instr_create(shader, nir_op_bcsel); + nir_alu_instr *sel = nir_alu_instr_create(shader, nir_op_b32csel); nir_src_copy(&sel->src[0].src, &if_stmt->condition, sel); /* Splat the condition to all channels */ memset(sel->src[0].swizzle, 0, sizeof sel->src[0].swizzle); diff --git a/src/compiler/nir/nir_opt_undef.c b/src/compiler/nir/nir_opt_undef.c index c26158dab7e..52c1d257e9f 100644 --- a/src/compiler/nir/nir_opt_undef.c +++ b/src/compiler/nir/nir_opt_undef.c @@ -38,7 +38,7 @@ static bool opt_undef_csel(nir_alu_instr *instr) { - if (instr->op != nir_op_bcsel && instr->op != nir_op_fcsel) + if (instr->op != nir_op_b32csel && instr->op != nir_op_fcsel) return false; assert(instr->dest.dest.is_ssa); diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 6860e7dc090..a0566b612cc 100644 --- a/src/compiler/spirv/vtn_alu.c +++ b/src/compiler/spirv/vtn_alu.c @@ -319,15 +319,15 @@ vtn_nir_alu_op_for_spirv_opcode(struct vtn_builder *b, case SpvOpShiftRightArithmetic: return nir_op_ishr; case SpvOpShiftLeftLogical: return nir_op_ishl; case SpvOpLogicalOr: return nir_op_ior; - case SpvOpLogicalEqual: return nir_op_ieq; - case SpvOpLogicalNotEqual: return nir_op_ine; + case SpvOpLogicalEqual: return nir_op_ieq32; + case SpvOpLogicalNotEqual: return nir_op_ine32; case SpvOpLogicalAnd: return nir_op_iand; case SpvOpLogicalNot: return nir_op_inot; case SpvOpBitwiseOr: return nir_op_ior; case SpvOpBitwiseXor: return nir_op_ixor; case SpvOpBitwiseAnd: return nir_op_iand; - case SpvOpSelect: return nir_op_bcsel; - case SpvOpIEqual: return nir_op_ieq; + case SpvOpSelect: return nir_op_b32csel; + case SpvOpIEqual: return nir_op_ieq32; case SpvOpBitFieldInsert: return nir_op_bitfield_insert; case SpvOpBitFieldSExtract: return nir_op_ibitfield_extract; @@ -339,27 +339,27 @@ vtn_nir_alu_op_for_spirv_opcode(struct vtn_builder *b, * the logical operator to use since they also need to check if operands are * ordered. */ - case SpvOpFOrdEqual: return nir_op_feq; - case SpvOpFUnordEqual: return nir_op_feq; - case SpvOpINotEqual: return nir_op_ine; - case SpvOpFOrdNotEqual: return nir_op_fne; - case SpvOpFUnordNotEqual: return nir_op_fne; - case SpvOpULessThan: return nir_op_ult; - case SpvOpSLessThan: return nir_op_ilt; - case SpvOpFOrdLessThan: return nir_op_flt; - case SpvOpFUnordLessThan: return nir_op_flt; - case SpvOpUGreaterThan: *swap = true; return nir_op_ult; - case SpvOpSGreaterThan: *swap = true; return nir_op_ilt; - case SpvOpFOrdGreaterThan: *swap = true; return nir_op_flt; - case SpvOpFUnordGreaterThan: *swap = true; return nir_op_flt; - case SpvOpULessThanEqual: *swap = true; return nir_op_uge; - case SpvOpSLessThanEqual: *swap = true; return nir_op_ige; - case SpvOpFOrdLessThanEqual: *swap = true; return nir_op_fge; - case SpvOpFUnordLessThanEqual: *swap = true; return nir_op_fge; - case SpvOpUGreaterThanEqual: return nir_op_uge; - case SpvOpSGreaterThanEqual: return nir_op_ige; - case SpvOpFOrdGreaterThanEqual: return nir_op_fge; - case SpvOpFUnordGreaterThanEqual: return nir_op_fge; + case SpvOpFOrdEqual: return nir_op_feq32; + case SpvOpFUnordEqual: return nir_op_feq32; + case SpvOpINotEqual: return nir_op_ine32; + case SpvOpFOrdNotEqual: return nir_op_fne32; + case SpvOpFUnordNotEqual: return nir_op_fne32; + case SpvOpULessThan: return nir_op_ult32; + case SpvOpSLessThan: return nir_op_ilt32; + case SpvOpFOrdLessThan: return nir_op_flt32; + case SpvOpFUnordLessThan: return nir_op_flt32; + case SpvOpUGreaterThan: *swap = true; return nir_op_ult32; + case SpvOpSGreaterThan: *swap = true; return nir_op_ilt32; + case SpvOpFOrdGreaterThan: *swap = true; return nir_op_flt32; + case SpvOpFUnordGreaterThan: *swap = true; return nir_op_flt32; + case SpvOpULessThanEqual: *swap = true; return nir_op_uge32; + case SpvOpSLessThanEqual: *swap = true; return nir_op_ige32; + case SpvOpFOrdLessThanEqual: *swap = true; return nir_op_fge32; + case SpvOpFUnordLessThanEqual: *swap = true; return nir_op_fge32; + case SpvOpUGreaterThanEqual: return nir_op_uge32; + case SpvOpSGreaterThanEqual: return nir_op_ige32; + case SpvOpFOrdGreaterThanEqual: return nir_op_fge32; + case SpvOpFUnordGreaterThanEqual: return nir_op_fge32; /* Conversions: */ case SpvOpQuantizeToF16: return nir_op_fquantize2f16; @@ -488,9 +488,9 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, } else { nir_op op; switch (src[0]->num_components) { - case 2: op = nir_op_bany_inequal2; break; - case 3: op = nir_op_bany_inequal3; break; - case 4: op = nir_op_bany_inequal4; break; + case 2: op = nir_op_b32any_inequal2; break; + case 3: op = nir_op_b32any_inequal3; break; + case 4: op = nir_op_b32any_inequal4; break; default: vtn_fail("invalid number of components"); } val->ssa->def = nir_build_alu(&b->nb, op, src[0], @@ -505,9 +505,9 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, } else { nir_op op; switch (src[0]->num_components) { - case 2: op = nir_op_ball_iequal2; break; - case 3: op = nir_op_ball_iequal3; break; - case 4: op = nir_op_ball_iequal4; break; + case 2: op = nir_op_b32all_iequal2; break; + case 3: op = nir_op_b32all_iequal3; break; + case 4: op = nir_op_b32all_iequal4; break; default: vtn_fail("invalid number of components"); } val->ssa->def = nir_build_alu(&b->nb, op, src[0], -- 2.19.1 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev