We also enable it in all of the NIR drivers.
Cc: Timothy Arceri <tarc...@itsqueeze.com>
Cc: Eric Anholt <e...@anholt.net>
Cc: Rob Clark <robdcl...@gmail.com>
Cc: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
---
src/amd/vulkan/radv_shader.c | 2 +
src/broadcom/compiler/vir.c | 2 +
src/compiler/Makefile.sources | 1 +
src/compiler/nir/meson.build | 1 +
src/compiler/nir/nir.h | 1 +
src/compiler/nir/nir_lower_bool_to_int32.c | 162 ++++++++++++++++++
.../drivers/freedreno/ir3/ir3_compiler_nir.c | 1 +
src/gallium/drivers/radeonsi/si_shader_nir.c | 2 +
src/gallium/drivers/vc4/vc4_program.c | 2 +
src/intel/compiler/brw_nir.c | 2 +
10 files changed, 176 insertions(+)
create mode 100644 src/compiler/nir/nir_lower_bool_to_int32.c
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index edeaefbc1a2..81f72d5b674 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -350,6 +350,8 @@ radv_shader_compile_to_nir(struct radv_device *device,
ac_lower_indirect_derefs(nir,
device->physical_device->rad_info.chip_class);
radv_optimize_nir(nir, flags &
VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
+ NIR_PASS_V(nir, nir_lower_bool_to_int32);
+
return nir;
}
diff --git a/src/broadcom/compiler/vir.c b/src/broadcom/compiler/vir.c
index 6b55b0e03bc..129afa4134a 100644
--- a/src/broadcom/compiler/vir.c
+++ b/src/broadcom/compiler/vir.c
@@ -729,6 +729,7 @@ uint64_t *v3d_compile_vs(const struct v3d_compiler
*compiler,
v3d_lower_nir_late(c);
v3d_optimize_nir(c->s);
+ NIR_PASS_V(c->s, nir_lower_bool_to_int32);
NIR_PASS_V(c->s, nir_convert_from_ssa, true);
v3d_nir_to_vir(c);
@@ -872,6 +873,7 @@ uint64_t *v3d_compile_fs(const struct v3d_compiler
*compiler,
v3d_lower_nir_late(c);
v3d_optimize_nir(c->s);
+ NIR_PASS_V(c->s, nir_lower_bool_to_int32);
NIR_PASS_V(c->s, nir_convert_from_ssa, true);
v3d_nir_to_vir(c);
diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index b65bb9b80b9..8f65f974ab8 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -230,6 +230,7 @@ NIR_FILES = \
nir/nir_lower_atomics_to_ssbo.c \
nir/nir_lower_bitmap.c \
nir/nir_lower_bit_size.c \
+ nir/nir_lower_bool_to_int32.c \
nir/nir_lower_clamp_color_outputs.c \
nir/nir_lower_clip.c \
nir/nir_lower_clip_cull_distance_arrays.c \
diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
index d8f65640004..5809551c9d4 100644
--- a/src/compiler/nir/meson.build
+++ b/src/compiler/nir/meson.build
@@ -113,6 +113,7 @@ files_libnir = files(
'nir_lower_alpha_test.c',
'nir_lower_atomics_to_ssbo.c',
'nir_lower_bitmap.c',
+ 'nir_lower_bool_to_int32.c',
'nir_lower_clamp_color_outputs.c',
'nir_lower_clip.c',
'nir_lower_clip_cull_distance_arrays.c',
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index b19138f9e61..7518ab5b94f 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2842,6 +2842,7 @@ void nir_lower_alpha_test(nir_shader *shader, enum
compare_func func,
bool alpha_to_one);
bool nir_lower_alu(nir_shader *shader);
bool nir_lower_alu_to_scalar(nir_shader *shader);
+bool nir_lower_bool_to_int32(nir_shader *shader);
bool nir_lower_load_const_to_scalar(nir_shader *shader);
bool nir_lower_read_invocation_to_scalar(nir_shader *shader);
bool nir_lower_phis_to_scalar(nir_shader *shader);
diff --git a/src/compiler/nir/nir_lower_bool_to_int32.c
b/src/compiler/nir/nir_lower_bool_to_int32.c
new file mode 100644
index 00000000000..8204f20d5b0
--- /dev/null
+++ b/src/compiler/nir/nir_lower_bool_to_int32.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "nir.h"
+
+static bool
+assert_ssa_def_is_not_1bit(nir_ssa_def *def, UNUSED void *unused)
+{
+ assert(def->bit_size > 1);
+ return true;
+}
+
+static bool
+rewrite_1bit_ssa_def_to_32bit(nir_ssa_def *def, void *_progress)
+{
+ bool *progress = _progress;
+ if (def->bit_size == 1) {
+ def->bit_size = 32;
+ *progress = true;
+ }
+ return true;
+}
+
+static bool
+lower_alu_instr(nir_alu_instr *alu)
+{
+ const nir_op_info *op_info = &nir_op_infos[alu->op];
+
+ switch (alu->op) {
+ case nir_op_imov:
+ case nir_op_vec2:
+ case nir_op_vec3:
+ case nir_op_vec4:
+ case nir_op_inot:
+ case nir_op_iand:
+ case nir_op_ior:
+ case nir_op_ixor:
+ /* These we expect to have booleans but the opcode doesn't change */
+ break;
+
+ case nir_op_f2b: alu->op = nir_op_f2b32; break;
+ case nir_op_i2b: alu->op = nir_op_i2b32; break;
+ case nir_op_b2f: alu->op = nir_op_b322f; break;
+ case nir_op_b2i: alu->op = nir_op_b322i; break;
+
+ case nir_op_flt: alu->op = nir_op_flt32; break;
+ case nir_op_fge: alu->op = nir_op_fge32; break;
+ case nir_op_feq: alu->op = nir_op_feq32; break;
+ case nir_op_fne: alu->op = nir_op_fne32; break;
+ case nir_op_ilt: alu->op = nir_op_ilt32; break;
+ case nir_op_ige: alu->op = nir_op_ige32; break;
+ case nir_op_ieq: alu->op = nir_op_ieq32; break;
+ case nir_op_ine: alu->op = nir_op_ine32; break;
+ case nir_op_ult: alu->op = nir_op_ult32; break;
+ case nir_op_uge: alu->op = nir_op_uge32; break;
+
+ case nir_op_ball_fequal2: alu->op = nir_op_b32all_fequal2; break;
+ case nir_op_ball_fequal3: alu->op = nir_op_b32all_fequal3; break;
+ case nir_op_ball_fequal4: alu->op = nir_op_b32all_fequal4; break;
+ case nir_op_bany_fnequal2: alu->op = nir_op_b32any_fnequal2; break;
+ case nir_op_bany_fnequal3: alu->op = nir_op_b32any_fnequal3; break;
+ case nir_op_bany_fnequal4: alu->op = nir_op_b32any_fnequal4; break;
+ case nir_op_ball_iequal2: alu->op = nir_op_b32all_iequal2; break;
+ case nir_op_ball_iequal3: alu->op = nir_op_b32all_iequal3; break;
+ case nir_op_ball_iequal4: alu->op = nir_op_b32all_iequal4; break;
+ case nir_op_bany_inequal2: alu->op = nir_op_b32any_inequal2; break;
+ case nir_op_bany_inequal3: alu->op = nir_op_b32any_inequal3; break;
+ case nir_op_bany_inequal4: alu->op = nir_op_b32any_inequal4; break;
+
+ case nir_op_bcsel: alu->op = nir_op_b32csel; break;
+
+ default:
+ assert(alu->dest.dest.ssa.bit_size > 1);
+ for (unsigned i = 0; i < op_info->num_inputs; i++)
+ assert(alu->src[i].src.ssa->bit_size > 1);
+ return false;
+ }
+
+ if (alu->dest.dest.ssa.bit_size == 1)
+ alu->dest.dest.ssa.bit_size = 32;
+
+ return true;
+}
+
+static bool
+nir_lower_bool_to_int32_impl(nir_function_impl *impl)
+{
+ bool progress = false;
+
+ nir_foreach_block(block, impl) {
+ nir_foreach_instr_safe(instr, block) {
+ switch (instr->type) {
+ case nir_instr_type_alu:
+ progress |= lower_alu_instr(nir_instr_as_alu(instr));
+ break;
+
+ case nir_instr_type_load_const: {
+ nir_load_const_instr *load = nir_instr_as_load_const(instr);
+ if (load->def.bit_size == 1) {
+ nir_const_value value = load->value;
+ for (unsigned i = 0; i < load->def.num_components; i++)
+ load->value.u32[i] = value.b[i] ? NIR_TRUE : NIR_FALSE;
+ load->def.bit_size = 32;
+ progress = true;
+ }
+ break;
+ }
+
+ case nir_instr_type_intrinsic:
+ case nir_instr_type_ssa_undef:
+ case nir_instr_type_phi:
+ case nir_instr_type_tex:
+ nir_foreach_ssa_def(instr, rewrite_1bit_ssa_def_to_32bit,
+ &progress);
+ break;
+
+ default:
+ nir_foreach_ssa_def(instr, assert_ssa_def_is_not_1bit, NULL);
+ }
+ }
+ }
+
+ if (progress) {
+ nir_metadata_preserve(impl, nir_metadata_block_index |
+ nir_metadata_dominance);
+ }
+
+ return progress;
+}
+
+bool
+nir_lower_bool_to_int32(nir_shader *shader)
+{
+ bool progress = false;
+
+ nir_foreach_function(function, shader) {
+ if (function->impl && nir_lower_bool_to_int32_impl(function->impl))
+ progress = true;
+ }
+
+ return progress;
+}
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index dde5e9c06cd..917d7cd04f1 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -178,6 +178,7 @@ compile_init(struct ir3_compiler *compiler,
/* this needs to be the last pass run, so do this here instead of
* in ir3_optimize_nir():
*/
+ NIR_PASS_V(ctx->s, nir_lower_bool_to_int32);
NIR_PASS_V(ctx->s, nir_lower_locals_to_regs);
NIR_PASS_V(ctx->s, nir_convert_from_ssa, true);
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 87ca0161b45..48cc0f5c349 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -825,6 +825,8 @@ si_lower_nir(struct si_shader_selector* sel)
NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
}
} while (progress);
+
+ NIR_PASS_V(sel->nir, nir_lower_bool_to_int32);
}
static void declare_nir_input_vs(struct si_shader_context *ctx,
diff --git a/src/gallium/drivers/vc4/vc4_program.c
b/src/gallium/drivers/vc4/vc4_program.c
index d3462c33be9..047567890ec 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -2384,6 +2384,8 @@ vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
vc4_optimize_nir(c->s);
+ NIR_PASS_V(c->s, nir_lower_bool_to_int32);
+
NIR_PASS_V(c->s, nir_convert_from_ssa, true);
if (vc4_debug & VC4_DEBUG_SHADERDB) {
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index cf5a4a96d67..431b2ab6b31 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -812,6 +812,8 @@ brw_postprocess_nir(nir_shader *nir, const struct
brw_compiler *compiler,
nir_print_shader(nir, stderr);
}
+ OPT(nir_lower_bool_to_int32);
+
OPT(nir_convert_from_ssa, true);
if (!is_scalar) {
--
2.19.1
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