Move the pipelined register access out of intel_batchbuffer into its
own utility file in preparation for replacing intel_batchbuffer. This
also gives us the opportunity to refactor a few similar routines for
writing registers, and so should prove useful in its own right.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/Makefile.sources | 2 +
src/mesa/drivers/dri/i965/brw_conditional_render.c | 1 +
src/mesa/drivers/dri/i965/brw_context.h | 12 ----
src/mesa/drivers/dri/i965/brw_draw.c | 1 +
src/mesa/drivers/dri/i965/brw_pipelined_register.c | 79 ++++++++++++++++++++++
src/mesa/drivers/dri/i965/brw_pipelined_register.h | 46 +++++++++++++
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 52 --------------
7 files changed, 129 insertions(+), 64 deletions(-)
create mode 100644 src/mesa/drivers/dri/i965/brw_pipelined_register.c
create mode 100644 src/mesa/drivers/dri/i965/brw_pipelined_register.h
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index a007440..be80246 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -90,6 +90,8 @@ i965_FILES = \
brw_packed_float.c \
brw_performance_monitor.c \
brw_pipe_control.c \
+ brw_pipelined_register.c \
+ brw_pipelined_register.h \
brw_primitive_restart.c \
brw_program.c \
brw_program.h \
diff --git a/src/mesa/drivers/dri/i965/brw_conditional_render.c
b/src/mesa/drivers/dri/i965/brw_conditional_render.c
index ffd10a6..962c1f1 100644
--- a/src/mesa/drivers/dri/i965/brw_conditional_render.c
+++ b/src/mesa/drivers/dri/i965/brw_conditional_render.c
@@ -35,6 +35,7 @@
#include "brw_context.h"
#include "brw_defines.h"
+#include "brw_pipelined_register.h"
#include "intel_reg.h"
static void
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 2c9ac9a..a9bc5e2 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1593,18 +1593,6 @@ void brw_store_register_mem64(struct brw_context *brw,
void brw_init_conditional_render_functions(struct dd_function_table
*functions);
bool brw_check_conditional_render(struct brw_context *brw);
-/** intel_batchbuffer.c */
-void brw_load_register_mem(struct brw_context *brw,
- uint32_t reg,
- brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
- uint32_t offset);
-void brw_load_register_mem64(struct brw_context *brw,
- uint32_t reg,
- brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
- uint32_t offset);
-
/*======================================================================
* brw_state_dump.c
*/
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 8ffc1c5..c819bb7 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -45,6 +45,7 @@
#include "brw_draw.h"
#include "brw_defines.h"
#include "brw_context.h"
+#include "brw_pipelined_register.h"
#include "brw_state.h"
#include "brw_vs.h"
diff --git a/src/mesa/drivers/dri/i965/brw_pipelined_register.c
b/src/mesa/drivers/dri/i965/brw_pipelined_register.c
new file mode 100644
index 0000000..9424e4a
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_pipelined_register.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright © 2010-2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "brw_context.h"
+#include "brw_pipelined_register.h"
+
+#include "intel_reg.h"
+
+static void
+load_sized_register_mem(struct brw_context *brw,
+ uint32_t reg,
+ brw_bo *bo,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t offset,
+ int size)
+{
+ int i;
+
+ /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
+ assert(brw->gen >= 7);
+
+ if (brw->gen >= 8) {
+ BEGIN_BATCH(4 * size);
+ for (i = 0; i < size; i++) {
+ OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2));
+ OUT_BATCH(reg + i * 4);
+ OUT_RELOC64(bo, read_domains, write_domain, offset + i * 4);
+ }
+ ADVANCE_BATCH();
+ } else {
+ BEGIN_BATCH(3 * size);
+ for (i = 0; i < size; i++) {
+ OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
+ OUT_BATCH(reg + i * 4);
+ OUT_RELOC(bo, read_domains, write_domain, offset + i * 4);
+ }
+ ADVANCE_BATCH();
+ }
+}
+
+void
+brw_load_register_mem(struct brw_context *brw,
+ uint32_t reg,
+ brw_bo *bo,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t offset)
+{
+ load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset,
1);
+}
+
+void
+brw_load_register_mem64(struct brw_context *brw,
+ uint32_t reg,
+ brw_bo *bo,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t offset)
+{
+ load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset,
2);
+}
diff --git a/src/mesa/drivers/dri/i965/brw_pipelined_register.h
b/src/mesa/drivers/dri/i965/brw_pipelined_register.h
new file mode 100644
index 0000000..c3dd02f
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_pipelined_register.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright © 2010-2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef BRW_PIPELINED_REGISTER_H
+#define BRW_PIPELINED_REGISTER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void brw_load_register_mem(struct brw_context *brw,
+ uint32_t reg,
+ brw_bo *bo,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t offset);
+void brw_load_register_mem64(struct brw_context *brw,
+ uint32_t reg,
+ brw_bo *bo,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t offset);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BRW_PIPELINED_REGISTER_H */
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 37dcc85..32b409a 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -449,55 +449,3 @@ intel_batchbuffer_data(struct brw_context *brw,
memcpy(brw->batch.map_next, data, bytes);
brw->batch.map_next += bytes >> 2;
}
-
-static void
-load_sized_register_mem(struct brw_context *brw,
- uint32_t reg,
- brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
- uint32_t offset,
- int size)
-{
- int i;
-
- /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
- assert(brw->gen >= 7);
-
- if (brw->gen >= 8) {
- BEGIN_BATCH(4 * size);
- for (i = 0; i < size; i++) {
- OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2));
- OUT_BATCH(reg + i * 4);
- OUT_RELOC64(bo, read_domains, write_domain, offset + i * 4);
- }
- ADVANCE_BATCH();
- } else {
- BEGIN_BATCH(3 * size);
- for (i = 0; i < size; i++) {
- OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
- OUT_BATCH(reg + i * 4);
- OUT_RELOC(bo, read_domains, write_domain, offset + i * 4);
- }
- ADVANCE_BATCH();
- }
-}
-
-void
-brw_load_register_mem(struct brw_context *brw,
- uint32_t reg,
- brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
- uint32_t offset)
-{
- load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset,
1);
-}
-
-void
-brw_load_register_mem64(struct brw_context *brw,
- uint32_t reg,
- brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
- uint32_t offset)
-{
- load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset,
2);
-}
--
2.5.0
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