On 4/9/09, Stephane Marchesin <marche...@icps.u-strasbg.fr> wrote: > On Thu, Apr 9, 2009 at 17:18, Alex Deucher <alexdeuc...@gmail.com> wrote: > > On 4/9/09, Stephane Marchesin <marche...@icps.u-strasbg.fr> wrote: > >> On Thu, Apr 9, 2009 at 08:49, Zou, Nanhai <nanhai....@intel.com> wrote: > >> > > >> > > >> > I have not been looking into gallium support yet. > >> > Are you working on software fallback or on some real hardware? > >> > >> > >> We have xvmc on top of g3dvl working on nv40-class hardware (and more > >> generically, it should work any card which has a gallium driver). > >> We've had this since last year's summer of code. Our main purpose is > >> to avoid reinventing the wheel with each driver... > >> > >> > >> > > >> > I am now working on HW accelerated media support for our chip(XVMC > etc), next plan is to support VAAPI. > >> > The code is now in our 2D dirver, in freedesktop.org xf86-video-driver > . The master branch has MC only implement, > >> > There is a branch xvmc-vld which support offload mpeg2 decode to GPU > from VLD entry. > >> > Media kernels running on GPU will do MC and IDCT and IQ, fix function > unit HW will do VLD decode. > >> > > >> > >> > >> Well, we don't have hw video decoding specs for nvidia/ati (and on > >> some hardware we don't even have any video decoding hw), so we use the > >> shaders for everything anyway. > > > > FWIW, MC is done using the 3D engine on our hardware, so MC should be > > able to be implemented now for those that are interested. r3xx+ use > > shaders. r1xx/r2xx have a couple special bits to flip in the 3D > > engine. idct is handled by a separate block what we hope to > > eventually release either code or docs for. > > > > For r100/r200 a specific implementation is going to be your only > option, but let's be honest, those cards can't do H.264. And these > days you can to H.262/263 just fine on the CPU anyway... >
Yeah. > That's my point: video codecs move too fast to be put into silicon, > and require too many resources to implement. So we should use shaders > and lay everything onto an API that takes care of the hardware > details. I completely agree. My point was simply that the info needed to implement MC is available for AMD chips. Alex ------------------------------------------------------------------------------ This SF.net email is sponsored by: High Quality Requirements in a Collaborative Environment. Download a free trial of Rational Requirements Composer Now! http://p.sf.net/sfu/www-ibm-com _______________________________________________ Mesa3d-dev mailing list Mesa3d-dev@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/mesa3d-dev
