I have checked to make sure the pm_cfg_obj.c is the one generated from my project, as well as the psu_init_gp.c. I have booted into Linux but fail any read/writes into the fabric. When performing the fpga loading from U-boot I am passing in the .bit file using “fpga loadb 0 <address> <size>” and I get a readout that confirms the loading of the bitstream. I also added some LED output to my fabric design to see if it comes up after programming, and the LEDs fail to light up… Which leads me to question what is responsible for powering up the PL island?
-Samuel From: Luca Ceresoli Sent: Tuesday, March 5, 2019 12:54 AM To: Samuel Berezhinskiy; meta-xilinx@yoctoproject.org Subject: Re: [meta-xilinx] ZCU104 U-boot SPL bootflow / PL programming Hi Samuel, On 04/03/19 21:37, Samuel Berezhinskiy wrote: > Hi, > > > > I’ve brought up the board in the sense that I can boot the SPL and make > it into U-Boot as well as being able to come up in Linux. But I seem to > have hit a major wall. After programming the FPGA from U-boot using the > typical command of “fpga loadb 0 <address> <size>” I’m unable to access > any of the AXI devices within the PL from U-boot or Linux, I seem to > just lock up the device, as if the PL is still either powered down or > Isolation is still enabled. Here are a few more checks that might be helpful. Did you rebuild your pmufw and U-Boot SPL with the pm_cfg_obj.c and psu_init_gpl.c specific for your FPGA design? Try disabling every PL peripheral in your device tree so Linux boots without hanging, then use devmem2 to access a register in your PL devices. Can you read/write registers? Also, are you pairing the right bitstream format with the right U-Boot command? 'fpga load' wants a .bin converted by [0] while (I think) 'fpga loadb' wants the bitstream file produced by Vivado. [0] https://github.com/topic-embedded-products/meta-topic/blob/master/recipes-bsp/fpga/fpga-bit-to-bin/fpga-bit-to-bin.py -- Luca
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