On Wed, Jan 03, 2024 at 08:50:43AM +0100, Lorenz (xha) wrote: > On Tue, Jan 02, 2024 at 08:32:00PM -0000, Stuart Henderson wrote: > > I can't say. Though I doubt there would much objection if it's clean and > > not a copy of a GPLv3-licensed upstream commit. > > what about this? > > i am not sure about the situation on arm64. it looks like newer gnu > assemblers don't like bti instructions unless explicitly enabled. > llvm seems to be using hint #34 for compatibility. > > is /usr/bin/as the GNU assembler on arm64 aswell?
There is no as(1) installed on arm64. -Otto > > Index: include/opcode/i386.h > =================================================================== > RCS file: /cvs/src/gnu/usr.bin/binutils-2.17/include/opcode/i386.h,v > retrieving revision 1.11 > diff -C5 -r1.11 i386.h > *** include/opcode/i386.h 9 Sep 2018 21:59:43 -0000 1.11 > --- include/opcode/i386.h 3 Jan 2024 07:35:49 -0000 > *************** > *** 1532,1541 **** > --- 1532,1545 ---- > > /* Intel PCID extension */ > {"invpcid", 2, 0x660f3882, X, CpuNEW|CpuNo64, > Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { > BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, > {"invpcid", 2, 0x660f3882, X, CpuNEW|Cpu64, > Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { > BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, > > + /* Intel Indirect Branch Tracking extensions */ > + {"endbr64", 0, 0xF30F1E, 0xFA, Cpu64, NoSuf|ImmExt, { 0, 0, 0 } }, > + {"endbr32", 0, 0xF30F1E, 0xFB, CpuNo64, NoSuf|ImmExt, { 0, 0, 0 } }, > + > /* sentinel */ > {NULL, 0, 0, 0, 0, 0, { 0, 0, 0} } > }; > #undef X > #undef NoSuf >