On Sun, Mar 15, 2009 at 1:36 PM, Jason Moxham <ja...@njkfrudils.plus.com> wrote: > > On Sunday 15 March 2009 17:29:30 Jason Martin wrote: >> > On Sunday 15 March 2009 17:03:51 Jason Martin wrote: >> >> Hi Guys, >> >> >> >> Sorry for the late reply, but I've been camping for the last couple >> >> days... >> >> >> >> I believe that I can rewrite the core2 code to avoid the lahf/sahf >> >> instructions without any performance lost. If there is still an >> >> interested or need, let me know and I'll have a go at it. >> >> >> >> --jwm >> > >> > I've got a 2c/l penryn add/sub but it does use lahf/sahf , probably also >> > 2c/l on core2.I have no idea if mine can written without lahf/sahf , I >> > still getting to grips with intel microarchitecture , compared with the >> > amd it's complicated. >> >> Is it in svn? If so, where should I look? >> > > No , I havent done the feedin/winddown code yet , just trying to get feel for > the arch.
Okay. Here's the idea if you want to try it: We use the lahf/sahf instruction because the Intel architecture has some weird dependencies on the carry bit with the inc/dec instructions (which results in pipeline stalls whenever inc/dec is used with adc/sbb). Torbjorn suggested using rcx as the counter register and using the jrcxz instruction for the loop control. You can use the lea instruction to modify rcx that way it doesn't touch the carry flag, and the lea instruction execute on an address port, saving an ALU port. --jwm --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "mpir-devel" group. To post to this group, send email to mpir-devel@googlegroups.com To unsubscribe from this group, send email to mpir-devel+unsubscr...@googlegroups.com For more options, visit this group at http://groups.google.com/group/mpir-devel?hl=en -~----------~----~----~----~------~----~------~--~---
