If cpuid.c doesn't compile then ./configure builds with x86_64-....

So it looks like that is not compiling on Jeff's machine.

Could stringinzing be missing?

Bill.

2009/4/16 Bill Hart <goodwillh...@googlemail.com>:
> Still scratching my head.
>
> Is there any chance you are using some kind of virtualisation or
> vmware or something on that machine. I mean that probably still
> wouldn't explain it, but we have had some misidentifications with kvm
> for example (though in that case /proc/cpuinfo clearly shows the wrong
> values).
>
> You certainly hit some interesting bugs Jeff. We should have done a
> longer RC to give time for you to report the result of your tests. We
> really appreciate you taking the time to do that.
>
> Bill.
>
> 2009/4/16 Jason Moxham <ja...@njkfrudils.plus.com>:
>>
>>
>> cpuinfo looks OK
>>
>> can you post the output from
>> ..../mpir-1.1/config.guess
>>
>> thanks
>> Jason
>>
>>
>> On Thursday 16 April 2009 02:16:44 Jeff Gilchrist wrote:
>>> On Wed, Apr 15, 2009 at 8:50 PM, Bill Hart <goodwillh...@googlemail.com>
>> wrote:
>>> > So yeah, the question is, how on earth did it misdetect that model.
>>> > The code looks totally solid and correct to me.
>>>
>>> I'm sure I linked with the correct MPIR, I'm linking to the static .a
>>> library.  Here is my /proc/cpuinfo
>>>
>>> processor       : 0
>>> vendor_id       : GenuineIntel
>>> cpu family      : 6
>>> model           : 23
>>> model name      : Intel(R) Xeon(R) CPU           E5405  @ 2.00GHz
>>> stepping        : 6
>>> cpu MHz         : 1995.005
>>> cache size      : 6144 KB
>>> physical id     : 0
>>> siblings        : 4
>>> core id         : 0
>>> cpu cores       : 4
>>> apicid          : 0
>>> fpu             : yes
>>> fpu_exception   : yes
>>> cpuid level     : 10
>>> wp              : yes
>>> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
>>> mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall
>>> nx lm constant_tsc pni monitor ds_cpl vmx tm2 cx16 xtpr lahf_lm
>>> bogomips        : 3992.94
>>> clflush size    : 64
>>> cache_alignment : 64
>>> address sizes   : 38 bits physical, 48 bits virtual
>>> power management:
>>>
>>>
>>
>>
>> >>
>>
>

--~--~---------~--~----~------------~-------~--~----~
You received this message because you are subscribed to the Google Groups 
"mpir-devel" group.
To post to this group, send email to mpir-devel@googlegroups.com
To unsubscribe from this group, send email to 
mpir-devel+unsubscr...@googlegroups.com
For more options, visit this group at 
http://groups.google.com/group/mpir-devel?hl=en
-~----------~----~----~----~------~----~------~--~---

Reply via email to