] > 8080A, but my attention fell on the IM 2 instruction... This uses register
] I
] > and a random number to jump to a location...
]
] Not random: it uses the number which is on the Z80 databus. But since this
] interrupt mode is not specified in the MSX standard, yes, it's kinda random
] (although on my computer it is always 255).
Dear all,
1) On a computer system that officially supports IM 2, the device generating
the interrupt request must put a device ID on the databus when the Z80
acknowledges the interrupt request.
2) On a computer system that does not support IM 2 (like the MSX), devices
are NOT allowed to put anything on the databus when the Z80 acknowledges the
interrupt request, since the Z80 will not expect anything there, so you might
get I/O conflicts if a device puts anything on the databus. Therefore, on the
MSX, no device will put anything on the databus.
3) On an MSX system, the databus is pulled-up with pull-up resistors, to have
a consistent state of the databus when no device writes anything to the
databus.
When you combine 2) and 3) you can safely conclude that any MSX computer has
255 on the databus at the moment that the Z80 reads it during IM 2.
So, it is sufficient to write your pointer to (I + 0xFF, I + 0x100), as shown
in Laurens code example.
Please keep in mind that some MSX emulators do not behave correctly when in
IM 2.
Please note also that on an MSX system IM 0 is equivalent to IM 1: during IM
0, the device must place an instruction opcode on the databus when the Z80
acknowledges the interrupt request. On the MSX, this value is per defition
0xff, because of the pull-up registers and the lack of a device that puts
anything on the databus. Opcode 0xff happens to be RST 38h, which is the same
instruction as the Z80 executes when receiving an interrupt in IM 1...
Kind regards,
Alex Wulms
Ps. I have used IM 2 as well on several occasions.
--
Alex Wulms/XelaSoft - MSX of anders NIX - Linux 4 ever
See my homepage for info on the *** XSA *** format
http://www.inter.nl.net/users/A.P.Wulms
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