David - Four are connected serially, updating 120 bits of 128 available. 
That group is updated every second. The fifth chip stands alone and only 30 
of 32 bits needs to be updated every 10ms. 

Greg - This is a much simpler application. From what I understand, which is 
not too much, it appears that separating CLK or LE or DATA will accomplish 
the same thing, and only one needs to be separated. Is this correct? 

The level shifter has two available lines so no additional hardware will be 
necessary.

On Saturday, October 17, 2015 at 7:33:47 PM UTC-4, gregebert wrote:
>
> Here's the approach I took. The PCB is a standalone 6-digit clock, but I 
> designed it so they can be abutted for as many digits as you wish. In my 
> case I'm using 3 boards for 14 digits. On each board, there are 2 clock 
> signals (CLK, CLKB) and I cascade the 2 HV5530's in series. The HV5530's 
> are clocked separately to ensure hold-time margin for the serial data. I 
> use a level-shifter from the 3.3V levels from the FPGA to the 12V levels 
> for the HV5530.
>
> There's no advantage for me to thread the serial data between boards, 
> because there's already a level-translator.
>
> To connect multiple boards, I provide a separate serial-data-in for each 
> board. All other signals are connected in parallel via a 10-conductor 
> ribbon cable. There is a termination resistor for the CLK and CLKB lines to 
> ground, and it will be populated on the last board at the end of the ribbon 
> cable.
>
> I should have provided a screenshot of the timing diagrams I have from the 
> simulations.
>

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