Separating CLK or DATA for individual HV5530's will, as you said, 
accomplish the same result. Separating LE is another option but you have to 
be careful to keep-track of what has been shifted.  It's not obvious from 
the diagrams I posted, but I actually have 4 serial data signals on the 
ribbon-cable, and I jumper a separate serial-data signal on each board 
(which limits my design to 4 boards or 24 digits with a single ribbon 
cable).

It's entirely possible to construct a single serial shift-chain, but you 
have to be careful about timing between cascaded HV5530's. According to the 
datasheet, the data hold-time is 10nsec. The min prop-delay of the 5530 is 
not specified, so you have to assume it's zero. In order to guarantee 
hold-time margin, the following equation applies:  Hold-margin = 
MinPropDelay - ClkSkew - MinHoldTime. In this case, even if you have zero 
CLK skew, you still have a 10nsec violation on the hold-time. Now, with 
real silicon the MinPropDelay is finite, and I *suspect* it's more than 
10nsec, but I'm not going to risk it. In my case, I created a second clock 
signal and I can guarantee hold-time margin through the sequencing of the 
signals from my FPGA.

Clock skew has a lot of subtleties. Yes, it's largely due to the 
board-trace flight-times, but it's also due to finite risetime of the clk 
signal itself and when each HV5530 determines the CLK is high or low. This 
will vary from device to device, and the effect is worsened with slow 
rise/fall times. Logic-level translators are quite slow, with delays in 
100's of nsec; I took no chances and used separate clks. I could have used 
an inverter to create the second CLK phase, but that was adding another IC 
and I already had a spare pin on the FPGA.

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