I checked into SVN my latest prom and spi controller. Browse it at https://svn.suug.ch/repos/opengraphics/main/trunk/rtl/spi_prom/
New features/updates include: 1) PROM block protection implemented 2) Updated prom test bench to cover more edge cases of memory protection 3) Fixed bugs found in the alternate controller and prom sim 4) Added conditional compilation to Makefile to use ISPLever ODDRXB buffer or Xilinx ODDRCPE in simulation. 5) Synthesizable alt controller: passes simulation of post-map in Synplify for XP6 and post-translate for Xilinx 3S4000. 6) Updated Petter's spi_test module to handle block protect. No changes needed to the spi_controller.v (nice job Petter!) To perform simulation using primitives, you'll have to update the Makefile's paths to point to the correct installation paths of Xilinx and ISPLever. See the README in ryans_version for details. I was unable to do post-map or post-par on Xilinx because the iverilig sdf module required for the timings isn't in the main branch yet. My current TODO list for the modules: Add check in alt prom controller to check whether read address requested was the last read performed and short-circuit the state machine. Redo CE_ output to be registered to prevent possibility of signal skew and glitches Something to note when we start doing synthesis, the XP6 should have a a 33 MHz constraint on the clock. Otherwise the timing reports show negative slack because the synthesizer tries to go for the highest frequency On the topic memory protection, I have read through the spec enough times that I feel I can give some input. Upon powerup, the flash's block protection defaults to full memory protection and memory writes are disabled. So to start writing to the flash, the following commands must be executed in order: Enable write to status register Write to status register (all 0's) Enable write to memory Chip erase (or sector/block erase depending on where you want to write) I'm not against having a jumper to disable writing, but hopefully this should assuage some fears about random signals on the bus rewriting the flash. I see the odds of random writes as very low. The threat of malicious code or a misbehaving prom driver, on the other hand, does make the jumper sound reasonable. -Ryan Changelog: ryans_version/Makefile: Created to ease development Includes targets for simulation using ISPLever and Xilinx DDR buffer ryans_version/README: Created to explain how to set up Makefile variables ryans_version/*.v, urkedal/spi_test_alt.v: Set `timescale to 1 ns / 1 ps since this was the assumed timescale ryans_version/spi_prom_ctrl_alt.v: Fixed enable/disable of aai_mode Added conditionals compilation for DDR buffer primitive: behavioral, ISPLever, and Xilinx Switched SCK from Mode 3 to Mode 0 clock so that ISPLever ODDRXB would work (I think there's a bug in the ODDRXB sim code. I have more info on when it comes up) Minor cosmetic changes to debug messages ryans_version/spi_prom_sim_alt.v: Added block protection! Fixed SO register to have high-impedance when CE_ is high Added more debug messages Fixed state transition for block erase ryans_version/spi_prom_ctrl_tb.v: Rewrote command sending to use tasks instead of a command queue. (Similar to Petter's TB) Added more thorough testing of all features of prom! I think I got em all covered now! The firsts tests cover the basics of reading and writing. The latter tests get into memory and block protection Prints happy smiley face if all tests pass! Added conditional "glbl" module required for Xilinx simulation ryans_version/spi_prom_ctrl_glue.v: Fixed glue code to send special write commands Expected protocol for special read commands such as status register and chip ID remain unknown. urkedal/spi_test_alt.v: Updated to include clearing status register due to block protection Modified write task to only execute one write at a time Added conditional compile to run test with spi_prom_ctrl_alt module _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
