On 6/26/06, Timothy Miller <[EMAIL PROTECTED]> wrote:
On 6/26/06, Ryan Osial <[EMAIL PROTECTED]> wrote:

> Something to note when we start doing synthesis, the XP6 should have a
> a 33 MHz constraint on the clock.  Otherwise the timing reports show
> negative slack because the synthesizer tries to go for the highest
> frequency

Negative slack means it's too slow.  You generally can't rely on the
optimizers in FPGA synthesis tools to help much with that, although
the P&R tools can place things carefully.  If the slack is positive,
that means your design is faster than it needs to be, and that's okay.


I know what you mean, but I'd like to clarify that first sentence.
Negative slack means the worst path's propagation delay is too long
for the required frequency.  Nearly any design could run at a 1 Hz
clock.

What I have found from past experience is that it's better to specify
a clock's frequency if it is known, especially when it is the
difference between the synth creating a design with positive vs
negative slack.  Sometimes the synth will give up on a design when it
can't improve the slack after a couple incremental optimizations.  In
other words, despite what the synth says, I don't trust a PAR of a
design with negative slack.

Here's the results of an unrestricted design where Synmplify chooses a
frequency vs me setting a frequency constraint.

Requested Frequency: 84.6 MHz, worst slack -3.542 ns
Requested Frequency: 33.0 MHz, worst slack 2.659 ns

The first tells me it will not work at the requested frequency.  It
_might_ work at a slower frequency.

The second tells me that tells design will work at 33 MHz and there's
some room to go faster.

If I wanted to know its maximum frequency, I'd perform a essentially a
binary search of the frequency space: try a frequency, and go up or
down depending on the slack.  I found 42 MHz with 0.265 slack as the
fastest it could produce.  That's about half as much as the synth
guessed was the fastest frequency.

By the way, I think this would be a good topic for a lesson after you
start into synthesis.
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