We're coming close to having prototype hardware for OGD1 boards, so
we're working to get pieces of RTL together for board testing.  We
need modules that are just functional enough to test to make sure all
of the signals on the board are there and working correctly.  As of
now, we have the following:

Some SPI controllers that we need to be sure are finished:

https://svn.suug.ch/repos/opengraphics/main/trunk/rtl/spi_prom/

We should use the simplest one, which I think is Petter's, IIRC.


A video controller that Patrick has nearly finished up:

https://svn.suug.ch/repos/opengraphics/main/trunk/rtl/vid_ctl/


And a couple of memory controllers:

https://svn.suug.ch/repos/opengraphics/main/trunk/rtl/mem_ctl/


The memory controller is the part I'm working on right now, and it's
the least tested of the lot, so I would like to get some assistance
with that.  The test bench needs to be expanded.  Right now, it shows
a write and a refresh behaving correctly, as far as I have fiddled
with it.  What we need to do is try every combination of actions and
make sure it always does the right thing.

Here is a PDF of a datasheet on DDR SDRAMs that has detailed
descriptions and timing diagrams:

http://download.micron.com/pdf/datasheets/dram/ddr/256MBDDRx4x8x16.pdf

This is the actual chip we're using (different timing numbers from the above):

http://www.samsung.com/products/semiconductor/DDR_DDR2/DDRSDRAM/Component/256Mbit/K4H561638F/K4H561638F.htm
http://www.samsung.com/Products/Semiconductor/DDR_DDR2/DDRSDRAM/Component/256Mbit/K4H561638F/ds_k4h56xx38f_tsop2_rev14.pdf

The one I'm working on is in the "tims" directory.  Petter's is the
other one.  I don't know how well-tested his is, but mine's been
through a bit of simulation.  Perhaps some can have a look at both
controllers and see if there's anything we can learn from both
designs.  But I also need some people to jump on this so we can get
the RTL ready to go when it's time to test the hardware.

Thanks.
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