On 10/29/06, Attila Kinali <[EMAIL PROTECTED]> wrote:
Please do not use asynchrone resets. Using asynchrone resets will in nearly all cases violate the setup and hold times. Even using a asynchron edge trigered reset like here, does only solve the hold time problem. The setup time violation is still there. Violation of either setup or hold time will result in a metastable behavior of the registers.
According to Howard, using async resets is the appropriate thing to do for an FPGA. They come "for free" with the available circuitry and they are supposed to behave correctly regardless of skew between reset and clock. For some reason, they're supposed to be better than sync resets. But I'm not sure why. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
