On Sun, 29 Oct 2006 11:30:24 -0400
"Timothy Miller" <[EMAIL PROTECTED]> wrote:
> According to Howard, using async resets is the appropriate thing to do
> for an FPGA. They come "for free" with the available circuitry and
> they are supposed to behave correctly regardless of skew between reset
> and clock. For some reason, they're supposed to be better than sync
> resets. But I'm not sure why.
Actualy it depends on the FPGA architecture and the syntehsizer.
FPGA Register have a direct reset input, most time configurable
to synchron and asychron.
Now if a synchron reset is used and the synthesiser does not use
the reset line of the register but instead "emulates" it by
using logic (how it would be done on an ASIC), then it's worse
than using async reset that uses the registers input.
Attila Kinali
--
Lotus Notes ist eine verteilte Datenbankapplikation,
als Sample ist eine miese Groupware dabei ;)
-- Lukas Beeler
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