Attila Kinali a écrit : > On Sun, 29 Oct 2006 11:30:24 -0400 > "Timothy Miller" <[EMAIL PROTECTED]> wrote: > > >> According to Howard, using async resets is the appropriate thing to do >> for an FPGA. They come "for free" with the available circuitry and >> they are supposed to behave correctly regardless of skew between reset >> and clock. For some reason, they're supposed to be better than sync >> resets. But I'm not sure why. >> > > Actualy it depends on the FPGA architecture and the syntehsizer. > > FPGA Register have a direct reset input, most time configurable > to synchron and asychron. > > Now if a synchron reset is used and the synthesiser does not use > the reset line of the register but instead "emulates" it by > using logic (how it would be done on an ASIC), then it's worse > than using async reset that uses the registers input. > > > Attila Kinali For the Xilinx Spartan3 FPGA with ISE as synthetizer the following is true, for other it could be false. If you use sync or async reset there is almost no difference when you control the return from the reset.
If an async reset is used you can't have a sync enable on the register else 1 of the 4 input of the LUT is used for the enable. In the other case if a sync reset is used with a sync enable all the input of the LUT are available and the dedicated circuit on the register is used for the enable. Except for that particularity there is no real difference between the async or sync reset. People still discuss what is the better reset, it's a still going discussion . The only important part is, to use across a design always the same reset and control the return from the reset state. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
