This is an automated email from Gerrit.
simon qian (simonqian.open...@gmail.com) just uploaded a new patch set to
Gerrit, which you can find at http://openocd.zylin.com/526
-- gerrit
commit 6822225b64b8af6fdc1e5b906d1a15dd3d65f05b
Author: Simon Qian <simonqian.open...@gmail.com>
Date: Sat Mar 17 15:21:59 2012 +0800
topic: add reset functions for SWD
Add swd_init_reset and swd_add_reset.
Add adi_v5_assert_reset and adi_v5_deassert_reset, and call them instead
of JTAG reset functions.
Change-Id: Ib2551c6fbb45513e0ae0dc331cfe3ee3f922298a
Signed-off-by: Simon Qian <simonqian.open...@gmail.com>
diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c
index 0c4169c..d05f9c1 100644
--- a/src/flash/nor/stellaris.c
+++ b/src/flash/nor/stellaris.c
@@ -1330,7 +1330,7 @@ COMMAND_HANDLER(stellaris_handle_recover_command)
LOG_ERROR("Can't recover Stellaris flash without SRST");
return ERROR_FAIL;
}
- jtag_add_reset(0, 1);
+ adi_v5_assert_reset();
for (int i = 0; i < 5; i++) {
retval = dap_to_swd(bank->target);
@@ -1343,7 +1343,7 @@ COMMAND_HANDLER(stellaris_handle_recover_command)
}
/* de-assert SRST */
- jtag_add_reset(0, 0);
+ adi_v5_deassert_reset();
retval = jtag_execute_queue();
/* wait 400+ msec ... OK, "1+ second" is simpler */
diff --git a/src/jtag/core.c b/src/jtag/core.c
index a36345b..84c43fa 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -606,6 +606,50 @@ void jtag_add_clocks(int num_cycles)
}
}
+void swd_add_reset(int req_srst)
+{
+ int new_srst = 0;
+
+ if (req_srst) {
+ if (!(jtag_reset_config & RESET_HAS_SRST)) {
+ LOG_ERROR("BUG: can't assert SRST");
+ jtag_set_error(ERROR_FAIL);
+ return;
+ }
+ new_srst = 1;
+ }
+
+ /* Maybe change TRST and/or SRST signal state */
+ if (jtag_srst != new_srst) {
+ int retval;
+
+ retval = interface_jtag_add_reset(0, new_srst);
+ if (retval != ERROR_OK)
+ jtag_set_error(retval);
+ else
+ retval = jtag_execute_queue();
+
+ if (retval != ERROR_OK) {
+ LOG_ERROR("TRST/SRST error");
+ return;
+ }
+ }
+
+ /* SRST resets everything hooked up to that signal */
+ if (jtag_srst != new_srst) {
+ jtag_srst = new_srst;
+ if (jtag_srst) {
+ LOG_DEBUG("SRST line asserted");
+ if (adapter_nsrst_assert_width)
+ jtag_add_sleep(adapter_nsrst_assert_width *
1000);
+ } else {
+ LOG_DEBUG("SRST line released");
+ if (adapter_nsrst_delay)
+ jtag_add_sleep(adapter_nsrst_delay * 1000);
+ }
+ }
+}
+
void jtag_add_reset(int req_tlr_or_trst, int req_srst)
{
int trst_with_tlr = 0;
@@ -1455,6 +1499,20 @@ int adapter_quit(void)
return ERROR_OK;
}
+int swd_init_reset(struct command_context *cmd_ctx)
+{
+ int retval = adapter_init(cmd_ctx);
+ if (retval != ERROR_OK)
+ return retval;
+
+ LOG_DEBUG("Initializing with hard SRST reset");
+
+ if (jtag_reset_config & RESET_HAS_SRST)
+ swd_add_reset(1);
+ swd_add_reset(0);
+ retval = jtag_execute_queue();
+ return retval;
+}
int jtag_init_reset(struct command_context *cmd_ctx)
{
diff --git a/src/jtag/swd.h b/src/jtag/swd.h
index 9a591f3..9041ce0 100644
--- a/src/jtag/swd.h
+++ b/src/jtag/swd.h
@@ -17,6 +17,9 @@
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
+#ifndef SWD_H
+#define SWD_H
+
/* Bits in SWD command packets, written from host to target
* first bit on the wire is START
*/
@@ -128,4 +131,9 @@ struct swd_driver {
int *(*trace)(bool swo);
};
+int swd_init_reset(struct command_context *cmd_ctx);
+void swd_add_reset(int req_srst);
+
bool transport_is_swd(void);
+
+#endif /* SWD_H */
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index c74df5e..b279b1f 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -33,6 +33,7 @@
#endif
#include "jtag.h"
+#include "swd.h"
#include "minidriver.h"
#include "interface.h"
#include "interfaces.h"
@@ -672,6 +673,7 @@ static int jim_jtag_arp_init(Jim_Interp *interp, int argc,
Jim_Obj *const *argv)
static int jim_jtag_arp_init_reset(Jim_Interp *interp, int argc, Jim_Obj
*const *argv)
{
+ int e = ERROR_OK;
Jim_GetOptInfo goi;
Jim_GetOpt_Setup(&goi, interp, argc-1, argv + 1);
if (goi.argc != 0) {
@@ -679,7 +681,11 @@ static int jim_jtag_arp_init_reset(Jim_Interp *interp, int
argc, Jim_Obj *const
return JIM_ERR;
}
struct command_context *context = current_command_context(interp);
- int e = jtag_init_reset(context);
+ if (transport_is_jtag())
+ e = jtag_init_reset(context);
+ else if (transport_is_swd())
+ e = swd_init_reset(context);
+
if (e != ERROR_OK) {
Jim_Obj *eObj = Jim_NewIntObj(goi.interp, e);
Jim_SetResultFormatted(goi.interp, "error: %#s", eObj);
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 1ef7c1a..5336c90 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -84,6 +84,27 @@ static uint32_t max_tar_block_size(uint32_t
tar_autoincr_block, uint32_t address
return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
}
+void adi_v5_assert_reset(void)
+{
+ enum reset_types jtag_reset_config = jtag_get_reset_config();
+
+ if (transport_is_jtag()) {
+ if (jtag_reset_config & RESET_SRST_PULLS_TRST)
+ jtag_add_reset(1, 1);
+ else
+ jtag_add_reset(0, 1);
+ } else if (transport_is_swd())
+ swd_add_reset(1);
+}
+
+void adi_v5_deassert_reset(void)
+{
+ if (transport_is_jtag())
+ jtag_add_reset(0, 0);
+ else if (transport_is_swd())
+ swd_add_reset(0);
+}
+
/***************************************************************************
* *
* DP and MEM-AP register access through APACC and DPACC *
@@ -977,10 +998,7 @@ int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
/* we need to assert reset */
if (jtag_reset_config & RESET_HAS_SRST) {
/* default to asserting srst */
- if (jtag_reset_config & RESET_SRST_PULLS_TRST)
- jtag_add_reset(1, 1);
- else
- jtag_add_reset(0, 1);
+ adi_v5_assert_reset();
} else {
LOG_DEBUG("SRST not configured");
dap_ap_select(dap, 0);
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 37b7771..a683337 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -32,6 +32,7 @@
*/
#include "arm_jtag.h"
+#include <jtag/swd.h>
/* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32()
* is no longer JTAG-specific
@@ -351,6 +352,10 @@ static inline uint8_t dap_ap_get_select(struct adiv5_dap
*swjdp)
return (uint8_t)(swjdp->ap_current >> 24);
}
+/* Reset assert and deassert */
+void adi_v5_assert_reset(void);
+void adi_v5_deassert_reset(void);
+
/* AP selection applies to future AP transactions */
void dap_ap_select(struct adiv5_dap *dap, uint8_t ap);
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 76e197c..a74b998 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -995,10 +995,7 @@ static int cortex_m3_assert_reset(struct target *target)
if (jtag_reset_config & RESET_HAS_SRST) {
/* default to asserting srst */
- if (jtag_reset_config & RESET_SRST_PULLS_TRST)
- jtag_add_reset(1, 1);
- else
- jtag_add_reset(0, 1);
+ adi_v5_assert_reset();
} else {
/* Use a standard Cortex-M3 software reset mechanism.
* We default to using VECRESET as it is supported on all
current cores.
@@ -1051,7 +1048,7 @@ static int cortex_m3_deassert_reset(struct target *target)
target_state_name(target));
/* deassert reset lines */
- jtag_add_reset(0, 0);
+ adi_v5_deassert_reset();
return ERROR_OK;
}
--
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