Hi, I'm re-posting my question from the user's list regarding my corrupted memory accesses on the devel list again:
I have a TI TMS570 / ARM Cortex R4 and troubles on byte and half-word accesses on the flash and SRAM area from the debug interface. Am 04.11.2013 22:30, schrieb Alex Züpke: > [...] On dumping the SRAM (big-endian mode), I get: > > > mdw 0x08000000 8 > 0x08000000: 000201f1 c0010cf1 ffffffea 00d01fe5 050000ea 08001000 > 1c3090e5 010c13e3 > > > mdh 0x08000000 16 > 0x08000000: 1c30 01f1 010c 0cf1 0002 ffea c001 1fe5 ffff 00ea 00d0 1000 > 0500 90e5 0800 13e3 > > > mdb 0x08000000 32 > 0x08000000: 1c 30 01 f1 01 0c 0c f1 00 02 ff ea c0 01 1f e5 ff ff 00 ea > 00 d0 10 00 05 00 90 e5 08 00 13 e3 > > Word access shows correct values, but halfword and byte accesses are > corrupted. It seems that the first half-words are always 64-bit "off" to > the right. > > When configuring the target to little endian mode, I get the same behaviour: > > [...] > > And I get similar results when dumping the flash memory. > > I followed the read implementation down to arm_adi_v5.c/mem_ap_read(), > and it seems that the data read from the DAP port is already corrupted. Could this be a limitation of the debug interface on the Cortex R4 core that it only supports 32-bit accesses via the debug port? Best regards, Alex ------------------------------------------------------------------------------ WatchGuard Dimension instantly turns raw network data into actionable security intelligence. It gives you real-time visual feedback on key security issues and trends. Skip the complicated setup - simply import a virtual appliance and go from zero to informed in seconds. http://pubads.g.doubleclick.net/gampad/clk?id=123612991&iu=/4140/ostg.clktrk _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
