On Mon, Feb 17, 2014 at 6:06 PM, Alex Züpke <[email protected]>wrote:
> Am 16.02.2014 00:51, schrieb Andreas Fritiofson:
>
>> On Fri, Jan 31, 2014 at 1:38 PM, Alex Züpke <[email protected]
>> <mailto:[email protected]>> wrote:
>>
>> Hi,
>>
>> I'm re-posting my question from the user's list regarding my corrupted
>> memory accesses on the devel list again:
>>
>> I have a TI TMS570 / ARM Cortex R4 and troubles on byte and half-word
>> accesses on the flash and SRAM area from the debug interface.
>>
>> Could this be a limitation of the debug interface on the Cortex R4
>> core
>> that it only supports 32-bit accesses via the debug port?
>>
>>
>> Can you check the debug log (-d3) whether the line containing "MEM_AP
>> Packed Transfers:" says enabled or disabled? There should be a
>> one-to-one correspondence between supporting packed transfers and
>> supporting less that word size accesses.
>>
>> /Andreas
>>
>
> It's enabled:
>
> Debug: 310 20 arm_adi_v5.c:866 ahbap_debugport_init(): MEM_AP Packed
> Transfers: enabled
>
So the ADIv5 spec says that it must also support 8 and 16-bit transfers.
Strange. That's about as far as I can go without some hardware to test on.
Let us know if you find the cause.
You might want to try forcing the packed transfer flag off and see if that
has any effect.
/Andreas
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