On Fri, Jan 31, 2014 at 1:38 PM, Alex Züpke <[email protected]>wrote:
>
> I have a TI TMS570 / ARM Cortex R4 and troubles on byte and half-word
> accesses on the flash and SRAM area from the debug interface.
>
> > I followed the read implementation down to arm_adi_v5.c/mem_ap_read(),
> > and it seems that the data read from the DAP port is already corrupted.
>
> Could this be a limitation of the debug interface on the Cortex R4 core
> that it only supports 32-bit accesses via the debug port?
>
>
I recently rewrote the MEM-AP access functions (i.e. mem_ap_read) to match
the ADIv5 spec regarding mapping of DAP register value to memory byte lane.
It works properly on at least ARMv7-M and I guess some ARMv7-A has been
tested too. I don't know about ARMv7-R and definitely not BE target. It
might be some optional feature in ADIv5 that is assumed by the code but not
implemented in your chip (even non-32 bit access is optional IIRC). If
that's the case, I'd consider it a bug because the target should be probed
for the available capabilities and the algorithm adapted accordingly.
First, are you sure you're reading through the MEM-AP and not using APB-AP
access? Because the latter *is* buggy, does not support byte/halfword
access and has endianness issues.
/Andreas
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