On Thu, Jul 17, 2014 at 08:03:16AM +1000, Angus Gratton wrote:
> > Does anyone has successful experience debugging nrf51 chip with FTDI based 
> > tool?
> 
> I've had the same experience as you, resistor hack working on other
> targets but not nrf51822. Didn't spend much time on it, as it works
> against my "have less wire mess" ultimate goal ;).
> 
> I put together an swd decoder for sigrok so when I get a chance I will
> have a look at the interactions on the wire, see if I can pick
> anything obvious. (I'll also release this decoder soon, I just want to
> make it a bit less hairy.)

I did a quick test just now.

The symptom is simple - the target never ACKs anything, just leaves
the bus high for the duration of the ACK cycle.

I looked at TDI & TDO simultaneously on an oscilloscope, and it's
clear that the only line driver is on the TDI side (ie
adapter->target.) I also increased the resistor I was using from 330R
to 1K in case the target line driver is really weak, same symptoms.

I read the nrf51822 datasheet and it had a bit to say about entering debug
mode:

> Debug interface mode is initiated by clocking one clock cycle on SWDCLK with 
> SWDIO=1. Due to delays
> caused by starting up the DAP's power domain, a minimum of 150 clock cycles 
> must be clocked at a speed
> of minimum 125 kHz on SWDCLK with SWDIO=1 to guaranty that the DAP is able to 
> capture a minimum of
> 50 clock cycles.

Hacked the swd.h header to send 200 high cycles as part of the
JTAG->SWD sequence, and hacked the ftdi.c driver to send at 1MHz
(formerly 1kHz), then tried 150kHz. Nothing changed. Note that I don't
think the stlink-v2 reset sequence quite meets the datasheet
requirements either, so it must be somewhat flexible...

Not quite sure what to test next apart from triple checking my wiring,
but I'll compare against the exact reset timings from the
st-link. There may be an undocumented delay required at some point
during the reset/enable cycle?


- Angus

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