Hi Andrii,

On Sun, Jul 20, 2014 at 02:47:02PM +0800, Andrii Anpilogov wrote:
> Label on the chip is:
> N51822
> QFAAC0
> 1322AW

We have the same C0 silicon revision then.

I went back and triple checked, running openocd clean built from
http://openocd.zylin.com/#/c/2223/ (commit
e10810b781dad21ddde22b8177d71a5a13456c5c) with my Olimex
ARM-USB-Tiny-H and everything definitely just works - 'reset init',
gdb, 'program blah.bin', etc.


On Sun, Jul 20, 2014 at 06:08:48PM +0800, Andrii Anpilogov wrote:
>         /* Set a low default */
> -       freq = mpsse_set_frequency(mpsse_ctx, 1000);
> +       freq = mpsse_set_frequency(mpsse_ctx, 150000);

So yours will not respond at all if reset at 1MHz, yes?

Can you share more details about exactly how your setup is wired -
what dev board, exact adapter, every connection, etc? Is there any
possibility something is connected to the debug lines that is
interfering, perhaps an unpowered device?

How is your board being powered? Are grounds connected between
debugger & dev board?

Any chance you can please take some oscilloscope traces of the waveforms at
the nrf SWD pins?


> +       if (reg == AP_REG_CSW)
> +               data &= ~CSW_DBGSWENABLE;
> +

This change didn't break anything for my setup. According to the ADIv5
specification clearing CSW_DBGSWENABLE disables software (ie onboard)
access to debug resources. I'm a bit confused about why it makes a
difference, but the comment in adi_v5_cmsis_dap does say it "causes
issues for some targets" ???


> +       /* this is a workaround to get polling working */
> +       jtag_add_reset(0, 0);
> +

On my adapter (olimex-usb-tiny-h) this is a No-Op, as
jtag_get_reset_config() returns null. Even if it did something, it can
only set the nTRST or nSRST signals, not issue an SWD line reset. Are
you sure it's a necessary change?


Angus

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