Hi Angus,
On 21 Jul, 2014, at 6:25 am, Angus Gratton <[email protected]> wrote:
> Hi Andrii,
>
> On Sun, Jul 20, 2014 at 02:47:02PM +0800, Andrii Anpilogov wrote:
>> Label on the chip is:
>> N51822
>> QFAAC0
>> 1322AW
>
> We have the same C0 silicon revision then.
>
> I went back and triple checked, running openocd clean built from
> http://openocd.zylin.com/#/c/2223/ (commit
> e10810b781dad21ddde22b8177d71a5a13456c5c) with my Olimex
> ARM-USB-Tiny-H and everything definitely just works - 'reset init',
> gdb, 'program blah.bin', etc.
>
git pull ssh://[email protected]:29418/openocd refs/changes/23/2223/1
doesn’t work for me at all:
Debug: 229 87 ftdi.c:981 ftdi_swd_run_queue(): JUNK DP read reg 0 = ffffffff
By adding "gdb_memory_map disable” to openocd config whit jtag_add_reset() and
CSW_DBGSWENABLE hack I can connect by gdb to openocd:
➜ ./openocd -f nrf51_test.cfg -c "gdb_memory_map disable" -c init -c "reset
init"
Open On-Chip Debugger 0.9.0-dev-00098-ge03eb89-dirty (2014-07-20-09:30)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.sourceforge.net/doc/doxygen/bugs.html
Info : FTDI SWD mode enabled
adapter speed: 1000 kHz
adapter_nsrst_delay: 10
cortex_m reset_config sysresetreq
Info : clock speed 1000 kHz
Info : SWD IDCODE 0x0bb11477
Info : nrf51.cpu: hardware has 4 breakpoints, 2 watchpoints
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0xc1000000 pc: 0x000101e4 msp: 0x20004000
Info : accepting 'gdb' connection on tcp/3333
But when I try load firmware it fails. Here is full openocd and gdb debug
output: http://pastebin.com/tUV6KgE7
>
> On Sun, Jul 20, 2014 at 06:08:48PM +0800, Andrii Anpilogov wrote:
>> /* Set a low default */
>> - freq = mpsse_set_frequency(mpsse_ctx, 1000);
>> + freq = mpsse_set_frequency(mpsse_ctx, 150000);
>
> So yours will not respond at all if reset at 1MHz, yes?
>
Correct.
> Can you share more details about exactly how your setup is wired -
> what dev board, exact adapter, every connection, etc? Is there any
> possibility something is connected to the debug lines that is
> interfering, perhaps an unpowered device?
>
There isn't digital schema. I’ll draw it and post it later.
On oscilloscope all signals look good and same adapter works fine for stm32f1x
as well as nRF51 kit works great with CMSIS-DAP adapter (except it’s extremely
slow).
> How is your board being powered? Are grounds connected between
> debugger & dev board?
>
Wiring is messy but by oscilloscope I can see that GND and VCC lines are clean
from any sort of significant noise.
VCC level is also good.
> Any chance you can please take some oscilloscope traces of the waveforms at
> the nrf SWD pins?
>
I’ll send it later today.
>
>> + if (reg == AP_REG_CSW)
>> + data &= ~CSW_DBGSWENABLE;
>> +
>
> This change didn't break anything for my setup. According to the ADIv5
> specification clearing CSW_DBGSWENABLE disables software (ie onboard)
> access to debug resources. I'm a bit confused about why it makes a
> difference, but the comment in adi_v5_cmsis_dap does say it "causes
> issues for some targets" ???
>
>
>> + /* this is a workaround to get polling working */
>> + jtag_add_reset(0, 0);
>> +
>
> On my adapter (olimex-usb-tiny-h) this is a No-Op, as
> jtag_get_reset_config() returns null. Even if it did something, it can
> only set the nTRST or nSRST signals, not issue an SWD line reset. Are
> you sure it's a necessary change?
>
I’ve found it strange as well. But it really make “reset init” command “stable”.
But combinations of jtag_add_reset() and CSW_DBGSWENABLE make “reset init”
command stage in my case.
It looks like “black magic”. I don’t like such moments.
Needs to be investigated more 8(
>
> Angus
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