IIRC, MRC/MCR thumb2 instr are 32bit, but they are reversed with the 1st half 
word in 15-0 of DGBITR and the 2nd half word in 31-16 of DGBITR.

I think the hard part is getting gdb to step through Aarch64 into Aarch32 (or 
vice versa).

If you look at my patch on how memory is access, its going through normal 
access mode instead of memory access mode.  to get both Aarch64 and Aarch32 to 
share the same code, it probably would be better to use the memory access mode. 
 I didn't extend it to use the faster memory access mode since all I needed at 
the time is for gdb to dump kernel stack and read variables.

David

________________________________________
From: Matthias Welwarsky <matth...@welwarsky.de>
Sent: Monday, September 12, 2016 12:39 AM
To: Duane Ellis
Cc: David Ung; openocd-devel@lists.sourceforge.net
Subject: Re: [OpenOCD-devel] OpenOCD Aarch64 support

On Sunday 11 September 2016 21:47:09 Matthias Welwarsky wrote:
> On Saturday 10 September 2016 23:27:15 Duane Ellis wrote:
> > > Do you know if there's a method to read registers that is usable in
> > > AArch32
> > > and -64 execution states?
> >
> > NO - the basic technique is the same Insert an opcode - and use the DCC to
> > transfer data, but the opcodes are totally different.
>
> OK.

Just noticed; MRC/MCR in AArch32 mode are compatible with ARM32. A1 == T1 and
A2 == T2 encoding. So they're not completely insane.

BR,
Matthias

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