Hi, I'm very much wondering if this feature is worth maintaining. Is it so useful that it's worth the considerable additional complexity for keeping the caches coherent? Flushing the caches is a very invasive action by a debugger and will considerably change the context under debug. If there isn't a compelling argument to keep it I'm much more in favor of removing it completely instead of trying fixing it.
BR. Matthias On Mittwoch, 1. August 2018 15:01:31 CEST gerrit wrote: > This is an automated email from Gerrit. > > Antonio Borneo (borneo.anto...@gmail.com) just uploaded a new patch set to > Gerrit, which you can find at http://openocd.zylin.com/4625 > > -- gerrit > > commit 8d73f142311fbf8c1d4624eafb93299a8061ddb4 > Author: Antonio Borneo <borneo.anto...@gmail.com> > Date: Thu Jul 26 17:53:25 2018 +0200 > > target/cortex_a: fix cache coherency with AHB read/write > > Some device uses AXI Coherency Extensions (ACE) to implement in HW > the coherency between the data caches of the cores and the memory > accesses through the DAP AHB/AXI port. > Unfortunately this setup is not common yet. For all the other > devices, it is important to guarantee the data cache coherency by > proper flush and invalidate SW calls. > In any case, the instruction cache has to be invalidated by SW, > also when ACE is available. > > Add instruction cache invalidate during AHB write and optional > (through auto_cache_enable) flush/invalidate of data cache during > AHB read/write. > > Change-Id: I18678d0495486a3cfae9454432e837b3eac6e64d > Signed-off-by: Antonio Borneo <borneo.anto...@gmail.com> > > diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c > index bc4aa33..409da15 100644 > --- a/src/target/cortex_a.c > +++ b/src/target/cortex_a.c > @@ -2749,6 +2749,10 @@ static int cortex_a_read_memory_ahb(struct target > *target, target_addr_t address LOG_DEBUG("Reading memory at address " > TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32, address, size, > count); > > + /* flush the data cache */ > + if (armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled) > + armv7a_l1_d_cache_clean_virt(target, address, size * count); > + > /* determine if MMU was enabled on target stop */ > if (!armv7a->is_armv7r) { > retval = cortex_a_mmu(target, &mmu_enabled); > @@ -2837,6 +2841,12 @@ static int cortex_a_write_memory_ahb(struct target > *target, target_addr_t addres LOG_DEBUG("Writing memory at address " > TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32, address, size, > count); > > + /* flush and invalidate the data cache */ > + if (armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled) > + armv7a_cache_flush_virt(target, address, size * count); > + /* invalidate instruction cache */ > + armv7a_l1_i_cache_inval_virt(target, address, size * count); > + > /* determine if MMU was enabled on target stop */ > if (!armv7a->is_armv7r) { > retval = cortex_a_mmu(target, &mmu_enabled); ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ OpenOCD-devel mailing list OpenOCD-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/openocd-devel
