Hm, just checked with current head on Nucleo-F767ZI via integrated ST-Link:
stm32f2x user_options 0xDFC, boot_add0 0x0080, boot_add1 0x0040,
so in dual-bank mode, after mass erase.

Programming the whole flash (2MBytes) with random data (flash write_bank 0 
random.bin) and verify after read back (flash read_bank 0 verify.bin) works 
flawlessly for me.

And same to second bank only works for me, too.

I'd suggest you try again without the 'erase' (do a mass erase instead and an 
erase check before), and then use flash write_bank with a binary (or ihex, 
srec) file.

Maybe your elf file has some 'unusual' properties.
 
BTW: Any sector protection set? 



---

** [tickets:#203] programming st_nucleo_f7 (stm32f767) bank 2 consistently 
fails**

**Status:** new
**Milestone:** 0.9.0
**Created:** Mon Aug 20, 2018 09:55 PM UTC by Cody Schafer
**Last Updated:** Tue Aug 21, 2018 05:00 PM UTC
**Owner:** nobody


In the `stm32f767zi` (on the nucleo-f767zi board), there is 2MiB of flash. When 
it is configured into dual bank mode (`stm32f2x options_write 0 0xDFC 0x0080 
0x0040`, presuming all other options are left at their defaults), using the 
`program` command to program the second bank (`bank1_start=0x0810_0000`, 
`bank2_start=0x0800_0000`) with the command `flash write_image fw.elf erase 
0x100000`, the execution consistently fails with the following output:

`openocd -f board/st_nucleo_f7.cfg`

```
> flash write_image fw.elf 0x100000       
Flash write discontinued at 0x081020c4, next section at 0x08120000
timed out while waiting for target halted
target halted due to debug-request, current mode: Handler HardFault
xPSR: 0x00000003 pc: 00000000 msp: 0xffffffe0
error waiting for target flash write algorithm
error writing to flash at address 0x08000000 at offset 0x00100000
```

This is using the embedded `ST-LINK`  included on the nucleo. The st-link 
firmware version is `V2J31M21`.

`fw.elf` has sections starting in bank1 of flash, which is why the offset is 
only the difference between bank1 and bank2.

The banks refered to here are banks in the stm32f7x sense, and are _not_ 
openocd flash banks.


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