I've created an elf file with the same section addresses/sizes, filled with
garbage, test_image reports the same figures as for yor file. No problem
whatsoever, programming and verification works ok for me. Checked with ST-Link
V2J30M19 and V2J31M21.
Other than the chip rev. (yours is Z, mine is A), I don't see any difference.
So either it's defective hardware, or ... your firmware does weird things like
fiddling with watchdogs, clocks, interrupts, sleep mode ...
This might explain your observations above.
Maybe add
reset_config srst_only srst_nogate connect_assert_srst
to your cfg or place an infinite loop at the very beginning of your startup
code (but take care not to change the length of the startup code, so that all
sections remain at precisely the same offsets).
---
** [tickets:#203] programming st_nucleo_f7 (stm32f767) bank 2 consistently
fails**
**Status:** new
**Milestone:** 0.9.0
**Created:** Mon Aug 20, 2018 09:55 PM UTC by Cody Schafer
**Last Updated:** Wed Aug 22, 2018 05:12 PM UTC
**Owner:** nobody
In the `stm32f767zi` (on the nucleo-f767zi board), there is 2MiB of flash. When
it is configured into dual bank mode (`stm32f2x options_write 0 0xDFC 0x0080
0x0040`, presuming all other options are left at their defaults), using the
`program` command to program the second bank (`bank1_start=0x0810_0000`,
`bank2_start=0x0800_0000`) with the command `flash write_image fw.elf erase
0x100000`, the execution consistently fails with the following output:
`openocd -f board/st_nucleo_f7.cfg`
```
> flash write_image fw.elf 0x100000
Flash write discontinued at 0x081020c4, next section at 0x08120000
timed out while waiting for target halted
target halted due to debug-request, current mode: Handler HardFault
xPSR: 0x00000003 pc: 00000000 msp: 0xffffffe0
error waiting for target flash write algorithm
error writing to flash at address 0x08000000 at offset 0x00100000
```
This is using the embedded `ST-LINK` included on the nucleo. The st-link
firmware version is `V2J31M21`.
`fw.elf` has sections starting in bank1 of flash, which is why the offset is
only the difference between bank1 and bank2.
The banks refered to here are banks in the stm32f7x sense, and are _not_
openocd flash banks.
---
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