This is an automated email from Gerrit. Tarek BOCHKATI ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/5861
-- gerrit commit ed3258923e26f02d75634d7b7b0cc3f3d446252c Author: Tarek BOCHKATI <[email protected]> Date: Wed Oct 14 14:14:09 2020 +0100 stm32h7x.cfg: alignment with RM0399 rev3 in RM0399 rev2, there was htese bits in DBGMCU_CR registers: - DBGSTBY_D3 : bit 7 - DBGSTOP_D3 : bit 8 these bits have been changed to reserved in rev3 Change-Id: I9d10d90e383795dc8e25a117d59fa065dc594610 Signed-off-by: Tarek BOCHKATI <[email protected]> diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg index 43a8b02..5220af3 100644 --- a/tcl/target/stm32h7x.cfg +++ b/tcl/target/stm32h7x.cfg @@ -149,8 +149,10 @@ $_CHIPNAME.cpu0 configure -event examine-end { stm32h7x_dbgmcu_mmw 0x004 0x00600000 0 # Enable debug during low power modes (uses more power) - # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3, D2 & D1 Domains - stm32h7x_dbgmcu_mmw 0x004 0x000001BF 0 + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D1 Domain + stm32h7x_dbgmcu_mmw 0x004 0x00000007 0 + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D2 Domain + stm32h7x_dbgmcu_mmw 0x004 0x00000038 0 # Stop watchdog counters during halt # DBGMCU_APB3FZ1 |= WWDG1 -- _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
