This is an automated email from Gerrit.
Weijie Gao (hackpas...@gmail.com) just uploaded a new patch set to Gerrit,
which you can find at http://openocd.zylin.com/6053
-- gerrit
commit b59ba8031a1b2c4082ab627886dcbae82688987e
Author: Weijie Gao <hackpas...@gmail.com>
Date: Tue Feb 2 11:04:01 2021 +0800
tcl/target: Add configuration for some MediaTek SoCs
Add configuration for some MediaTek SoCs:
ARM: MT7622 MT7629
MIPS: MT7620 MT7621 MT7628
Change-Id: I37d30da21d360c1102b4b054fb6f301ae623dc98
Signed-off-by: Weijie Gao <hackpas...@gmail.com>
diff --git a/tcl/target/mediatek/memc.tcl b/tcl/target/mediatek/memc.tcl
new file mode 100644
index 0000000..c4b2686
--- /dev/null
+++ b/tcl/target/mediatek/memc.tcl
@@ -0,0 +1,31 @@
+#
+# Memory controller helpers
+#
+
+source [find target/mediatek/mmio.tcl]
+
+proc ddr_init {cfgs dq_dly dqs_dly} {
+ mmio_clrbits_32 0xb0000304 0x20000000
+ mww 0xb0000348 [lindex $cfgs 2]
+ mww 0xb000034c [lindex $cfgs 3]
+ mww 0xb0000350 [lindex $cfgs 4]
+ mww 0xb0000360 $dq_dly
+ mww 0xb0000364 $dqs_dly
+ mww 0xb0000340 [lindex $cfgs 0]
+ mww 0xb0000344 [expr ([lindex $cfgs 1] & (~0x30000)) | 0x20000]
+ mmio_clrsetbits_32 0xb0000314 0xffffff 1
+ mmio_setbits_32 0xb0000310 0x10
+}
+
+proc sdr_init {cfgs rows cols} {
+ mww 0xb0000300 [lindex $cfgs 0]
+ mww 0xb0000304 [expr [lindex $cfgs 1] | (($rows & 3) << 16) | (($cols & 3)
<< 20)]
+
+ set init_done 0
+ while {$pll_locked == 0} {
+ set init_done [expr [mmio_readfield_32 0xb0000304 30 1]]
+ }
+
+ mmio_clrsetbits_32 0xb0000314 0xffffff 1
+ mmio_setbits_32 0xb0000310 0x10
+}
diff --git a/tcl/target/mediatek/mmio.tcl b/tcl/target/mediatek/mmio.tcl
new file mode 100644
index 0000000..44c73db
--- /dev/null
+++ b/tcl/target/mediatek/mmio.tcl
@@ -0,0 +1,25 @@
+#
+# MMIO register r/w helpers
+#
+
+proc mmio_read_32 {addr} {
+ set result ""
+ mem2array result 32 $addr 1
+ return $result(0)
+}
+
+proc mmio_clrbits_32 {addr bits} {
+ mww $addr [expr [mmio_read_32 $addr] & (~($bits))]
+}
+
+proc mmio_setbits_32 {addr bits} {
+ mww $addr [expr [mmio_read_32 $addr] | $bits]
+}
+
+proc mmio_clrsetbits_32 {addr clr set} {
+ mww $addr [expr ([mmio_read_32 $addr] & (~($clr))) | $set]
+}
+
+proc mmio_readfield_32 {addr shift mask} {
+ return [expr ([mmio_read_32 $addr] >> $shift) & $mask]
+}
diff --git a/tcl/target/mediatek/mt7620.cfg b/tcl/target/mediatek/mt7620.cfg
new file mode 100644
index 0000000..e614d2e
--- /dev/null
+++ b/tcl/target/mediatek/mt7620.cfg
@@ -0,0 +1,110 @@
+#
+# The MediaTek MT7620 is a highly integrated 2T2R 802.11n wireless network
+# router SoC.
+#
+# Product page:
+# https://www.mediatek.com/products/homeNetworking/mt7620n-a
+#
+# Specifications:
+# - MIPS24KEc @ 580 MHz
+# - 64KB I-Cache and 32KB D-Cache
+#
+
+source [find target/mediatek/mmio.tcl]
+source [find target/mediatek/memc.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME mt7620
+}
+
+jtag newtap ${_CHIPNAME} cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id
0x1635224f
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create ${_TARGETNAME}0 mips_m4k -endian little -chain-position
${_CHIPNAME}.cpu
+
+proc cpu_pll_init {} {
+ # Set init CPU clock to 480MHz
+ mmio_clrsetbits_32 0xb0000058 0x02000000 0x01000000
+
+ # Enable software control of CPU PLL
+ mmio_setbits_32 0xb0000054 0x80000000
+
+ # CPU PLL power down
+ mmio_setbits_32 0xb0000058 0x04000000
+
+ # PLL configuration PLL_MULT_RATIO = 5, PLL_DIV_RATIO = 0 (+1) SSC_SWING =
7
+ mmio_clrsetbits_32 0xb0000054 0x04070ff0 0x00050070
+
+ # CPU PLL power up
+ mmio_clrbits_32 0xb0000058 0x04000000
+
+ # Wait for CPU PLL locked
+ set pll_locked 0
+ while {$pll_locked == 0} {
+ set pll_locked [expr [mmio_readfield_32 0xb0000058 23 1]]
+ }
+
+ # Set final CPU clock source
+ mmio_clrbits_32 0xb0000058 0x03000000
+
+ # Adjust CPU clock
+ mmio_clrsetbits_32 0xb000003c 0x00001f1f 0x00000101
+}
+
+proc dram_init {size} {
+ set ddr1_cfgs_8mb { 0x34A1EB94 0x20262324 0x28000033 0x00000002
0x00000000 }
+ set ddr1_cfgs_16mb { 0x34A1EB94 0x202A2324 0x28000033 0x00000002
0x00000000 }
+ set ddr1_cfgs_32mb { 0x34A1E5CA 0x202E2324 0x28000033 0x00000002
0x00000000 }
+ set ddr1_cfgs_64mb { 0x3421E5CA 0x20322324 0x28000033 0x00000002
0x00000000 }
+ set ddr1_cfgs_128mb { 0x241B05CA 0x20362334 0x28000033 0x00000002
0x00000000 }
+
+ set ddr2_cfgs_32mb { 0x2519E2E5 0x222E2323 0x68000C43 0x00000416
0x0000000A }
+ set ddr2_cfgs_64mb { 0x249AA2E5 0x22322323 0x68000C43 0x00000416
0x0000000A }
+ set ddr2_cfgs_128mb { 0x249B42E5 0x22362323 0x68000C43 0x00000416
0x0000000A }
+ set ddr2_cfgs_256mb { 0x249CE2E5 0x223A2323 0x68000C43 0x00000416
0x0000000A }
+
+ set sdr_cfgs { 0x51B283B3 0xC00003A9 }
+
+ set ddr_type [expr [mmio_readfield_32 0xb0000010 4 3]]
+
+ mmio_setbits_32 0xb0000034 0x400
+ sleep 200
+ mmio_clrbits_32 0xb0000034 0x400
+
+ if { $ddr_type == 1 } {
+ if { $size == 8 } {
+ ddr_init $ddr1_cfgs_8mb 0x88888888 0x88888888
+ } elseif { $size == 16 } {
+ ddr_init $ddr1_cfgs_16mb 0x88888888 0x88888888
+ } elseif { $size == 32 } {
+ ddr_init $ddr1_cfgs_32mb 0x88888888 0x88888888
+ } elseif { $size == 64 } {
+ ddr_init $ddr1_cfgs_64mb 0x88888888 0x88888888
+ } elseif { $size == 128 } {
+ ddr_init $ddr1_cfgs_128mb 0x88888888 0x88888888
+ }
+ } elseif { $ddr_type == 2 } {
+ if { $size == 32 } {
+ ddr_init $ddr2_cfgs_32mb 0x88888888 0x88888888
+ } elseif { $size == 64 } {
+ ddr_init $ddr2_cfgs_64mb 0x88888888 0x88888888
+ } elseif { $size == 128 } {
+ ddr_init $ddr2_cfgs_128mb 0x88888888 0x88888888
+ } elseif { $size == 256 } {
+ ddr_init $ddr2_cfgs_256mb 0x88888888 0x88888888
+ }
+ } else {
+ if { $size == 8 } {
+ sdr_init $sdr_cfgs 1 0
+ } elseif { $size == 16 } {
+ sdr_init $sdr_cfgs 1 1
+ } elseif { $size == 32 } {
+ sdr_init $sdr_cfgs 2 1
+ } elseif { $size == 64 } {
+ sdr_init $sdr_cfgs 2 2
+ }
+ }
+}
diff --git a/tcl/target/mediatek/mt7621.cfg b/tcl/target/mediatek/mt7621.cfg
new file mode 100644
index 0000000..6872916
--- /dev/null
+++ b/tcl/target/mediatek/mt7621.cfg
@@ -0,0 +1,40 @@
+#
+# The MediaTek MT7621 is a highly integrated network processor suitable for
+# 802.11ac wireless router/AP platform, LTE cat4/5, Internet Service Router
+# and Home Security Gateway.
+#
+# Product page:
+# https://www.mediatek.com/products/homeNetworking/mt7621
+#
+# Specifications:
+# - Dual-core MIPS1004Kc @ 880 MHz (2 VPEs per core)
+# - 32KB L1 I-Cache and 32KB L2 D-Cache
+# - 256KB unified L2 Cache
+#
+# Note:
+# Each core can be halted/resumed individually.
+# When a VPE is halted, the another VPE within the same core will also be
+# halted automatically.
+#
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME mt7621
+}
+
+jtag newtap ${_CHIPNAME} cm -irlen 5 -ircapture 0x1 -irmask 0x1f
-expected-id 0x1762124f
+jtag newtap ${_CHIPNAME}c1v1 cpu -irlen 5 -ircapture 0x1 -irmask 0x1f
-expected-id 0x1762124f
+jtag newtap ${_CHIPNAME}c1v0 cpu -irlen 5 -ircapture 0x1 -irmask 0x1f
-expected-id 0x1762024f
+jtag newtap ${_CHIPNAME}c0v1 cpu -irlen 5 -ircapture 0x1 -irmask 0x1f
-expected-id 0x1762124f
+jtag newtap ${_CHIPNAME}c0v0 cpu -irlen 5 -ircapture 0x1 -irmask 0x1f
-expected-id 0x1762024f
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create ${_TARGETNAME}3 mips_m4k -endian little -chain-position
${_CHIPNAME}c1v1.cpu -defer-examine
+target create ${_TARGETNAME}2 mips_m4k -endian little -chain-position
${_CHIPNAME}c1v0.cpu
+target create ${_TARGETNAME}1 mips_m4k -endian little -chain-position
${_CHIPNAME}c0v1.cpu -defer-examine
+target create ${_TARGETNAME}0 mips_m4k -endian little -chain-position
${_CHIPNAME}c0v0.cpu
+
+# only core0 vpe0 is active after power-up
+targets ${_TARGETNAME}0
diff --git a/tcl/target/mediatek/mt7622.cfg b/tcl/target/mediatek/mt7622.cfg
new file mode 100644
index 0000000..da56822
--- /dev/null
+++ b/tcl/target/mediatek/mt7622.cfg
@@ -0,0 +1,60 @@
+#
+# The MediaTek MT7622 is a highly integrated wireless network router SoC for
+# for high wireless performance, home entertainment and home automation.
+#
+# Product page:
+# https://www.mediatek.com/products/homenetworking/mt7622
+#
+# Specifications:
+# - Dual-core ARM Cortex-A53 MPCoreTM @ 1.35GHz
+# − 32KB L1 I-Cache and 32KB L1 D-Cache
+# − 512KB unified L2 Cache
+# − NEON/FPU
+#
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME mt7622
+}
+
+if { [info exists DAP_TAPID] } {
+ set _DAP_TAPID $DAP_TAPID
+} else {
+ set _DAP_TAPID 0x4ba00477
+}
+
+set _COREBASE {0x80810000 0x80910000}
+set _CTIBASE {0x80820000 0x80920000}
+set _CORES 2
+
+# declare the one JTAG tap to access the DAP
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_DAP_TAPID -ignore-version -enable
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# declare the main application cores
+set _TARGETNAME $_CHIPNAME.cpu
+set _smp_command ""
+
+for { set _core 0 } { $_core < $_CORES } { incr _core 1 } {
+
+ cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [lindex $_CTIBASE
$_core] -ap-num 1
+
+ set _command "target create ${_TARGETNAME}$_core aarch64 \
+ -dap $_CHIPNAME.dap -coreid $_core \
+ -cti cti$_core -dbgbase [lindex $_COREBASE $_core]"
+
+ if { $_core != 0 } {
+ # non-boot core examination may fail
+ set _command "$_command -defer-examine"
+ set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+ } else {
+ set _smp_command "target smp ${_TARGETNAME}$_core"
+ }
+
+ eval $_command
+}
+
+eval $_smp_command
+
+targets ${_TARGETNAME}0
diff --git a/tcl/target/mediatek/mt7628.cfg b/tcl/target/mediatek/mt7628.cfg
new file mode 100644
index 0000000..eb29419
--- /dev/null
+++ b/tcl/target/mediatek/mt7628.cfg
@@ -0,0 +1,118 @@
+#
+# The MediaTek MT7628 is a highly integrated 2T2R 802.11n wireless network
+# router SoC.
+#
+# Product page:
+# https://www.mediatek.com/products/homeNetworking/mt7628k-n-a
+#
+# Specifications:
+# - MIPS24KEc @ 575/580 MHz
+# - 64KB I-Cache and 32KB D-Cache
+#
+# Note:
+# This configuration also applies to MediaTek MT7688
+#
+
+source [find target/mediatek/mmio.tcl]
+source [find target/mediatek/memc.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME mt7628
+}
+
+jtag newtap ${_CHIPNAME} cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id
0x1762824f
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create ${_TARGETNAME}0 mips_m4k -endian little -chain-position
${_CHIPNAME}.cpu
+
+proc cpu_pll_init {} {
+ set _rom_normal 0
+ set check_count 1000
+
+ while {$_rom_normal == 0 && $check_count != 0} {
+ set _rom_normal [expr [mmio_read_32 0xb0000028] & 1]
+ set check_count [expr $check_count - 1]
+ sleep 1
+ }
+
+ if { $_rom_normal != 0 } {
+ # DIS_BBP_SLEEP, EN_BBP_CLK
+ mmio_clrsetbits_32 0xb000002c 0x3 0xc
+ } else {
+ # CPU_PLL_FROM_XTAL
+ mmio_clrsetbits_32 0xb000002c 0x2 0x1
+ }
+
+ # Adjust CPU clock
+ mmio_clrsetbits_32 0xb0000440 0x00000f0f 0x00000101
+}
+
+proc dram_init {size} {
+ set ddr1_cfgs_8mb { 0x34A1EB94 0x20262324 0x28000033 0x00000002
0x00000000 }
+ set ddr1_cfgs_16mb { 0x34A1EB94 0x202A2324 0x28000033 0x00000002
0x00000000 }
+ set ddr1_cfgs_32mb { 0x34A1E5CA 0x202E2324 0x28000033 0x00000002
0x00000000 }
+ set ddr1_cfgs_64mb { 0x3421E5CA 0x20322324 0x28000033 0x00000002
0x00000000 }
+ set ddr1_cfgs_128mb { 0x241B05CA 0x20362334 0x28000033 0x00000002
0x00000000 }
+
+ set ddr2_cfgs_32mb { 0x2519E2E5 0x222E2323 0x68000C43 0x00000452
0x0000000A }
+ set ddr2_cfgs_64mb { 0x249AA2E5 0x22322323 0x68000C43 0x00000452
0x0000000A }
+ set ddr2_cfgs_128mb { 0x249B42E5 0x22362323 0x68000C43 0x00000452
0x0000000A }
+ set ddr2_cfgs_256mb { 0x249CE2E5 0x223A2323 0x68000C43 0x00000452
0x0000000A }
+
+ set ddr_type [expr [mmio_read_32 0xb0000010] & 1]
+
+ mmio_setbits_32 0xb0000034 0x400
+ sleep 200
+ mmio_clrbits_32 0xb0000034 0x400
+
+ if { $ddr_type == 1 } {
+ mww 0xb0001100 0x81c00000
+ mww 0xb000110c 0x10060
+ sleep 50
+ mww 0xb000110c 0x50060
+ mww 0xb0001104 0x5182
+ mww 0xb0001704 0xc0c
+ mww 0xb000170c 0x202
+ mww 0xb0001710 0x60001000
+ mww 0xb0001714 0x707
+ mww 0xb0001718 0x60001000
+ mww 0xb000171c 0xc0c
+
+ if { $size == 8 } {
+ ddr_init $ddr1_cfgs_8mb 0x8282 0x8383
+ } elseif { $size == 16 } {
+ ddr_init $ddr1_cfgs_16mb 0x8282 0x8383
+ } elseif { $size == 32 } {
+ ddr_init $ddr1_cfgs_32mb 0x8282 0x8383
+ } elseif { $size == 64 } {
+ ddr_init $ddr1_cfgs_64mb 0x8282 0x8383
+ } elseif { $size == 128 } {
+ ddr_init $ddr1_cfgs_128mb 0x8282 0x8383
+ }
+ } else {
+ mww 0xb0001100 0x81c00000
+ mww 0xb000110c 0x10020
+ sleep 50
+ mww 0xb000110c 0x50020
+ mww 0xb0001104 0x5182
+ mww 0xb0001704 0xc0c
+ mww 0xb000170c 0x202
+ mww 0xb0001710 0x60001000
+ mww 0xb0001714 0x404
+ mww 0xb0001718 0x60001000
+ mww 0xb000171c 0xc0c
+
+ if { $size == 32 } {
+ ddr_init $ddr2_cfgs_32mb 0x8282 0x8383
+ } elseif { $size == 64 } {
+ ddr_init $ddr2_cfgs_64mb 0x8282 0x8383
+ } elseif { $size == 128 } {
+ ddr_init $ddr2_cfgs_128mb 0x8282 0x8383
+ } elseif { $size == 256 } {
+ ddr_init $ddr2_cfgs_256mb 0x8282 0x8383
+ }
+ }
+}
diff --git a/tcl/target/mediatek/mt7629.cfg b/tcl/target/mediatek/mt7629.cfg
new file mode 100644
index 0000000..ca8816b
--- /dev/null
+++ b/tcl/target/mediatek/mt7629.cfg
@@ -0,0 +1,53 @@
+#
+# The MediaTek MT7629 is a highly integrated wireless network router SoC for
+# for high wireless performance, home entertainment and home automation.
+#
+# Specifications:
+# - Dual-core ARM Cortex-A7 MPCoreTM @ 1.25GHz
+# − 32KB L1 I-Cache and 32KB L1 D-Cache
+# - 256KB unified L2 Cache
+#
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME mt7629
+}
+
+if { [info exists DAP_TAPID] } {
+ set _DAP_TAPID $DAP_TAPID
+} else {
+ set _DAP_TAPID 0x4ba00477
+}
+
+set _COREBASE {0x80810000 0x80812000}
+set _CORES 2
+
+# declare the one JTAG tap to access the DAP
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_DAP_TAPID -enable
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# declare the main application cores
+set _TARGETNAME $_CHIPNAME.cpu
+set _smp_command ""
+
+for { set _core 0 } { $_core < $_CORES } { incr _core 1 } {
+
+ set _command "target create ${_TARGETNAME}$_core cortex_a \
+ -dap $_CHIPNAME.dap -coreid $_core \
+ -dbgbase [lindex $_COREBASE $_core]"
+
+ if { $_core != 0 } {
+ # non-boot core examination may fail
+ set _command "$_command -defer-examine"
+ set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+ } else {
+ set _smp_command "target smp ${_TARGETNAME}$_core"
+ }
+
+ eval $_command
+}
+
+eval $_smp_command
+
+targets ${_TARGETNAME}0
--
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