Sorry for being quiet for a while, I asked my friends for help and now I also have a board with a STM32H743, I'll try it later.
> On 11 Jul 2023, at 10:11, Tomas Vanek <tom_...@users.sourceforge.net> wrote: > > It is a problem in the ARM licensed silicon so it may or more likely may not > be described in ST device errata. > ARM doc: > https://developer.arm.com/documentation/EPM064408/latest/ > 702596 > Single stepping Cortex-M7 enters pending exception handler > > and check OpenOCD debug log what product revision is the Cortex-M7 core. The test starts like this: 1: Test command: /Users/ilg/Work/xpack-dev-tools-build/openocd-0.12.0-2/darwin-x64/application/bin/openocd "-c" "gdb_port disabled" "-c" "tcl_port disabled" "-c" "telnet_port disabled" "-f" "interface/stlink.cfg" "-f" "target/stm32f7x.cfg" "-c" "program rtos-apis-test.elf verify" "-c" "arm semihosting enable" "-c" "arm semihosting_cmdline rtos-apis-test" "-c" "reset" 1: Test timeout computed to be: 10000000 1: xPack Open On-Chip Debugger 0.12.0+dev-01252-g56fd04832-dirty (2023-07-10-11:36) 1: Licensed under GNU GPL v2 1: For bug reports, read 1: http://openocd.org/doc/doxygen/bugs.html 1: Info : auto-selecting first available session transport "hla_swd". To override use 'transport select <transport>'. 1: Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD 1: Info : clock speed 2000 kHz 1: Info : STLINK V2J41M27 (API v2) VID:PID 0483:3752 1: Info : Target voltage: 3.243713 1: Info : [stm32f7x.cpu] Cortex-M7 r1p0 processor detected > If OpenOCD detects M7 r0p1 (or r0p0), enables lot of workarounds by setting > cortex_m->maskints_erratum. > Be aware that there is no complete workaround for this erratum, so OpenOCD > just minimizes the time window > when single stepping can enter a pending interrupt handler. It could cause > the OpenOCD host speed dependency you > described. So it should not be affected. Liviu
