This is an automated email from Gerrit. "Jérôme Pouiller <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9399
-- gerrit commit 0955aff2cb9618e5b4d21e2d33186568257a694e Author: Jérôme Pouiller <[email protected]> Date: Fri Jan 23 13:38:01 2026 +0100 tcl/target: Add support for most of the Silabs Series 2 Let's introduce one file per EFR32/EFM32 family so the final user does not have to find the tweaks for every parts. Change-Id: I544282be675e3dbf9194da615d7f8865631612a2 Signed-off-by: Jérôme Pouiller <[email protected]> diff --git a/tcl/target/efr32xg21.cfg b/tcl/target/efr32xg21.cfg new file mode 100644 index 0000000000..acb6244e43 --- /dev/null +++ b/tcl/target/efr32xg21.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (c) 2026 Silicon Laboratories Inc. +# +# Silicon Labs EFM32PG21/EFR32xG21 target + +set FLASHBASE 0x00000000 +source [find target/efr32-series2.cfg] diff --git a/tcl/target/efr32xg22.cfg b/tcl/target/efr32xg22.cfg new file mode 100644 index 0000000000..9fbd28e9bc --- /dev/null +++ b/tcl/target/efr32xg22.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (c) 2026 Silicon Laboratories Inc. +# +# Silicon Labs EFM32PG22/EFR32xG22 target + +set FLASHBASE 0x00000000 +source [find target/efr32-series2.cfg] diff --git a/tcl/target/efr32xg23.cfg b/tcl/target/efr32xg23.cfg new file mode 100644 index 0000000000..c6384f4ab8 --- /dev/null +++ b/tcl/target/efr32xg23.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (c) 2026 Silicon Laboratories Inc. +# +# Silicon Labs EFM32PG23/EFR32xG23 target + +set FLASHBASE 0x08000000 +source [find target/efr32-series2.cfg] diff --git a/tcl/target/efr32xg24.cfg b/tcl/target/efr32xg24.cfg new file mode 100644 index 0000000000..a2bd084cff --- /dev/null +++ b/tcl/target/efr32xg24.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (c) 2026 Silicon Laboratories Inc. +# +# Silicon Labs EFM32PG24/EFR32xG24 target + +set FLASHBASE 0x08000000 +source [find target/efr32-series2.cfg] diff --git a/tcl/target/efr32xg25.cfg b/tcl/target/efr32xg25.cfg new file mode 100644 index 0000000000..905f28b74b --- /dev/null +++ b/tcl/target/efr32xg25.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (c) 2026 Silicon Laboratories Inc. +# +# Silicon Labs EFM32PG25/EFR32xG25 target + +set FLASHBASE 0x08000000 +source [find target/efr32-series2.cfg] diff --git a/tcl/target/efr32xg26.cfg b/tcl/target/efr32xg26.cfg new file mode 100644 index 0000000000..322212057d --- /dev/null +++ b/tcl/target/efr32xg26.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (c) 2026 Silicon Laboratories Inc. +# +# Silicon Labs EFM32PG26/EFR32xG26 target + +set FLASHBASE 0x08000000 +source [find target/efr32-series2.cfg] diff --git a/tcl/target/efr32xg28.cfg b/tcl/target/efr32xg28.cfg new file mode 100644 index 0000000000..0862d803d2 --- /dev/null +++ b/tcl/target/efr32xg28.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (c) 2026 Silicon Laboratories Inc. +# +# Silicon Labs EFM32PG28/EFR32xG28 target + +set FLASHBASE 0x08000000 +source [find target/efr32-series2.cfg] diff --git a/tcl/target/efr32xg29.cfg b/tcl/target/efr32xg29.cfg new file mode 100644 index 0000000000..ff7bcfa211 --- /dev/null +++ b/tcl/target/efr32xg29.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (c) 2026 Silicon Laboratories Inc. +# +# Silicon Labs EFM32PG29/EFR32xG29 target + +set FLASHBASE 0x08000000 +source [find target/efr32-series2.cfg] --
