This is an automated email from Gerrit. "Jérôme Pouiller <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9400
-- gerrit commit e537fe3105e0a6d137713ae8dec1782e07f9649f Author: Jérôme Pouiller <[email protected]> Date: Fri Jan 16 17:37:49 2026 +0100 tcl/target: Add support for EFR32xG27 EFR32xG27 devices do not support VC_CORERESET (Vector Catch on Core Reset). The standard SYSRESETREQ also resets the debug interface, causing the core to exit reset before OpenOCD can set up vector catch. Add a custom reset procedure using the Flash Patch and Breakpoint (FPB) unit. 1. Halt the core via direct DHCSR access 2. Read the reset vector from flash 3. Set an FPB breakpoint at the reset vector 4. Issue SYSRESETREQ 5. Core halts when it hits the breakpoint at reset vector Change-Id: I056397f33737ff1ccee0fd702c2edf992512c01f Signed-off-by: Jérôme Pouiller <[email protected]> diff --git a/tcl/target/efr32xg27.cfg b/tcl/target/efr32xg27.cfg new file mode 100644 index 0000000000..a60ba04291 --- /dev/null +++ b/tcl/target/efr32xg27.cfg @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (c) 2026 Silicon Laboratories Inc. +# +# Silicon Labs EFM32PG27/EFR32xG27 target + +set FLASHBASE 0x08000000 +source [find target/efr32-series2.cfg] + +# VC_CORERESET does not work on xG27. Use FPB breakpoint at reset vector +# instead. This procedure implements a custom reset that: +# 1. Halts the core +# 2. Sets an FPB breakpoint at the reset vector +# 3. Issues SYSRESETREQ +# 4. Core halts when it hits the breakpoint at reset vector +proc efr32xg27_reset {} { + set target [target current] + set dap [$target cget -dap] + + # Configure CSW for 32-bit access, auto-increment off + $dap apreg 0 0x00 0x23000002 + + # Halt core by writing to DHCSR (0xE000EDF0) + set halt_cmd [expr {0xA05F0000 | 0x3}] ;# DBGKEY | C_DEBUGEN | C_HALT + $dap apreg 0 0x04 0xE000EDF0 + $dap apreg 0 0x0C $halt_cmd + + # Wait for S_HALT bit + for {set i 0} {$i < 50} {incr i} { + $dap apreg 0 0x04 0xE000EDF0 + set dhcsr_val [$dap apreg 0 0x0C] + if {$dhcsr_val & 0x20000} { + break + } + $dap apreg 0 0x0C $halt_cmd + sleep 20 + } + + # Read reset vector from flash + $dap apreg 0 0x04 0x08000004 + set reset_vector [$dap apreg 0 0x0C] + + if {$reset_vector == 0xFFFFFFFF || $reset_vector == 0} { + echo "Warning: Could not read reset vector" + return + } + + # Clear Thumb bit for breakpoint address + set bp_addr [expr {$reset_vector & 0xFFFFFFFE}] + echo [format "EFR32xG27: Setting breakpoint at reset vector 0x%08X" $bp_addr] + + # Save current FPB state + $dap apreg 0 0x04 0xE0002000 + set fp_ctrl [$dap apreg 0 0x0C] + $dap apreg 0 0x04 0xE0002008 + set fp_comp0 [$dap apreg 0 0x0C] + + # Enable FPB (FP_CTRL = 0x3) + $dap apreg 0 0x04 0xE0002000 + $dap apreg 0 0x0C 0x3 + + # Set breakpoint at reset vector (FP_COMP0 = addr | 1) + $dap apreg 0 0x04 0xE0002008 + $dap apreg 0 0x0C [expr {$bp_addr | 1}] + + # Issue SYSRESETREQ (AIRCR = VECTKEY | SYSRESETREQ) + $dap apreg 0 0x04 0xE000ED0C + $dap apreg 0 0x0C 0x05FA0004 + + # Wait for reset and halt at breakpoint + sleep 100 + + # Restore FPB state + catch { + $dap apreg 0 0x04 0xE0002000 + $dap apreg 0 0x0C [expr {$fp_ctrl | 2}] + $dap apreg 0 0x04 0xE0002008 + $dap apreg 0 0x0C $fp_comp0 + } +} + +$_TARGETNAME configure -event reset-assert { + efr32xg27_reset +} --
