Alan Carvalho de Assis wrote: > Hi Duane, > > On 5/27/09, Duane Ellis <open...@duaneellis.com> wrote: > >> FYI - most of UrJTAG's support is *BOUNDARY*SCAN* - based external chip >> flash programing via boundary scan >> >> > Arggg, then it will not help too much! No - actually it is useful for other purposes... a method to flash something - however slow it may be - is better then no method to flash something, or the ability to flash a board with a CPU you do not support.
UrJTAG's approach is to read the BSDL file -figure out the bus structure - and read and write memory locations. One could - create some interesting things. And - most importantly - it can be used to create a "debug tool" useful for board bring up. For example - you have a new board you are trying to bring up - nothing works - you can use BSDL - to wiggle/pulse a pin and probe it out. I'd be *REALLY* happy if I could create a JTAG hardware test - using BSDL files... Granted, for "production purposes" - it would be very slow. But - for "simple prototype work" - it would be great. Sure, production hardware jtag tests that take 10 minutes are *TOO*LONG* - however - the ability to perform a hardware jtag test on a *SIMPLE* 5 piece prototype build - is another matter. I'd let it run over lunch - or while I am in a meeting, when I'm back I know know my prototype is "mostly working" :-) YEA!!!!! That does not yet exist. -Duane. _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
