On Tuesday 25 August 2009, Øyvind Harboe wrote:
> 01_openocd_beagle.patch is problematic because it modifies the behavior
> for *all* targets.
>
> Thoughts?
I see no problem ... TAP_RESET is a stable state, and
JTAG adapters are allowed to let TCK run freely there.
> We need some more general mechanism. OpenOCD shouldn't
> litter it's lower layers w/target specific hacks.
I'd agree if we had any evidence that this could cause
trouble ... equally, we don't want to clutter things
with special cases that can interact poorly.
Note that some PXAs wanted extra TCK cycles too.
- Dave
======= CUT HERE
Partial fix for TAPs which need extra TCK cycles in the TAP_RESET
state. This relies on the fact that TAP_RESET is a stable state,
where TCK may run freely, and always issues those TCK cycles.
This doesn't address entry to TAP_RESET using TRST. Fixing that
will require calling jtag_add_tlr() after deasserting TRST.
---
src/jtag/core.c | 9 +++++++++
1 file changed, 9 insertions(+)
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -469,6 +469,15 @@ void jtag_add_tlr(void)
{
jtag_prelude(TAP_RESET);
jtag_set_error(interface_jtag_add_tlr());
+
+ /*
+ * Add a bunch of clocks after TLR entry to force SWD reset (newer
+ * ARM cores; just in case, ~50 cycles), switch on ICEpick power
+ * domains (for some TI parts, ~100 cycles), etc. TAP_RESET is a
+ * stable state, so this must be harmless to all JTAG controllers.
+ */
+ jtag_set_error(interface_jtag_add_runtest(100, TAP_RESET));
+
jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
}
Partial fix for TAPs which need extra TCK cycles in the TAP_RESET
state. This relies on the fact that TAP_RESET is a stable state,
where TCK may run freely, and always issues those TCK cycles.
This doesn't address entry to TAP_RESET using TRST. Fixing that
will require calling jtag_add_tlr() after deasserting TRST.
---
src/jtag/core.c | 9 +++++++++
1 file changed, 9 insertions(+)
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -469,6 +469,15 @@ void jtag_add_tlr(void)
{
jtag_prelude(TAP_RESET);
jtag_set_error(interface_jtag_add_tlr());
+
+ /*
+ * Add a bunch of clocks after TLR entry to force SWD reset (newer
+ * ARM cores; just in case, ~50 cycles), switch on ICEpick power
+ * domains (for some TI parts, ~100 cycles), etc. TAP_RESET is a
+ * stable state, so this must be harmless to all JTAG controllers.
+ */
+ jtag_set_error(interface_jtag_add_runtest(100, TAP_RESET));
+
jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
}
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