Sorry, I took another look and saw what you were talking about and how to
correct for it. Here's another version that addresses that issue.
// Dean Glazeski
On Thu, Dec 17, 2009 at 10:56 PM, Dean Glazeski <dngl...@gmail.com> wrote:
> Oh, I didn't see that. This patch can be ignored then. It just looks so
> similar :).
>
> // Dean Glazeski
>
>
>
> On Thu, Dec 17, 2009 at 10:29 PM, David Brownell <davi...@pacbell.net>wrote:
>
>> On Tuesday 15 December 2009, Dean Glazeski wrote:
>> > I noticed the NAND erase function was doing page command stuff, so I
>> pulled
>> > the redundant code out. Patch is attached
>>
>> This doesn't look right. Consider the 16 Gbit large page chip
>> I happen to have on some boards here:
>>
>> - read/write of 2KB page uses 5 byte addressing
>> - erase of 128KB block uses 3 byte addressping
>>
>> You're making both use the 5 byte addressing ... basically, if
>> this is going to be shared, the erase commands shouldn't be
>> writing column addresses, just row addresses.
>>
>> - Dave
>>
>>
>>
>>
>
From 2bb284a568f936f47e2a638e80c1554f94f5e860 Mon Sep 17 00:00:00 2001
From: Dean Glazeski <dngl...@gmail.com>
Date: Tue, 15 Dec 2009 23:57:18 -0600
Subject: [PATCH 1/4] Use NAND page command in erase.
Updated the NAND erase function to use the NAND page command function. This
also updates the command function to support the erase command and uses the NAND
poll function when the NAND ready function doesn't exist for the controller.
---
src/flash/nand/core.c | 50 +++++++++++-------------------------------------
1 files changed, 12 insertions(+), 38 deletions(-)
diff --git a/src/flash/nand/core.c b/src/flash/nand/core.c
index d52cf5d..044f4e2 100644
--- a/src/flash/nand/core.c
+++ b/src/flash/nand/core.c
@@ -537,48 +537,16 @@ int nand_erase(struct nand_device *nand, int first_block, int last_block)
for (i = first_block; i <= last_block; i++)
{
/* Send erase setup command */
- nand->controller->command(nand, NAND_CMD_ERASE1);
-
page = i * (nand->erase_size / nand->page_size);
+ retval = nand_page_command(nand, page, NAND_CMD_ERASE1, false);
- /* Send page address */
- if (nand->page_size <= 512)
- {
- /* row */
- nand->controller->address(nand, page & 0xff);
- nand->controller->address(nand, (page >> 8) & 0xff);
-
- /* 3rd cycle only on devices with more than 32 MiB */
- if (nand->address_cycles >= 4)
- nand->controller->address(nand, (page >> 16) & 0xff);
-
- /* 4th cycle only on devices with more than 8 GiB */
- if (nand->address_cycles >= 5)
- nand->controller->address(nand, (page >> 24) & 0xff);
- }
- else
- {
- /* row */
- nand->controller->address(nand, page & 0xff);
- nand->controller->address(nand, (page >> 8) & 0xff);
-
- /* 3rd cycle only on devices with more than 128 MiB */
- if (nand->address_cycles >= 5)
- nand->controller->address(nand, (page >> 16) & 0xff);
- }
-
- /* Send erase confirm command */
- nand->controller->command(nand, NAND_CMD_ERASE2);
-
- retval = nand->controller->nand_ready ?
- nand->controller->nand_ready(nand, 1000) :
- nand_poll_ready(nand, 1000);
- if (!retval) {
+ if (ERROR_OK != retval) {
LOG_ERROR("timeout waiting for NAND flash block erase to complete");
return ERROR_NAND_OPERATION_TIMEOUT;
}
- if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
+ retval = nand_read_status(nand, &status);
+ if (retval != ERROR_OK)
{
LOG_ERROR("couldn't read status");
return ERROR_NAND_OPERATION_FAILED;
@@ -758,11 +726,17 @@ int nand_page_command(struct nand_device *nand, uint32_t page,
nand->controller->command(nand, NAND_CMD_READSTART);
}
+ if (NAND_CMD_ERASE1 == cmd) {
+ /* verify erase commands. */
+ nand->controller->command(nand, NAND_CMD_ERASE2);
+ }
+
if (nand->controller->nand_ready) {
- if (!nand->controller->nand_ready(nand, 100))
+ if (!nand->controller->nand_ready(nand, 1000))
return ERROR_NAND_OPERATION_TIMEOUT;
} else {
- alive_sleep(1);
+ if (!nand_poll_ready(nand, 1000))
+ return ERROR_NAND_OPERATION_TIMEOUT;
}
return ERROR_OK;
--
1.6.5.2
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