Dne Pá 18. prosince 2009 06:11:23 Dean Glazeski napsal(a):
> Sorry, I took another look and saw what you were talking about and how to
> correct for it.  Here's another version that addresses that issue.
> 
> // Dean Glazeski
> 
> On Thu, Dec 17, 2009 at 10:56 PM, Dean Glazeski <dngl...@gmail.com> wrote:
> > Oh, I didn't see that.  This patch can be ignored then.  It just looks so
> > similar :).
> >
> > // Dean Glazeski
> >
> > On Thu, Dec 17, 2009 at 10:29 PM, David Brownell <davi...@pacbell.net>wrote:
> >> On Tuesday 15 December 2009, Dean Glazeski wrote:
> >> > I noticed the NAND erase function was doing page command stuff, so I
> >>
> >> pulled
> >>
> >> > the redundant code out.  Patch is attached
> >>
> >> This doesn't look right.  Consider the 16 Gbit large page chip
> >> I happen to have on some boards here:
> >>
> >>  - read/write of 2KB page uses 5 byte addressing
> >>  - erase of 128KB block uses 3 byte addressping
> >>
> >> You're making both use the 5 byte addressing ... basically, if
> >> this is going to be shared, the erase commands shouldn't be
> >> writing column addresses, just row addresses.
> >>
> >> - Dave
> 

Why are you incrementing the timeout from 100 to 1000 in the nand_page_command 
? 
btw. please stop top-posting.
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