On 06:58 Fri 06 May , Øyvind Harboe wrote: > >> +# The chip may run @ 32khz, so set a really low JTAG speed > >> +adapter_khz 8 > > this is the wrong place it's not board specific but soc specific > > > > tcl/target/at91rm9200.cfg > > Perhaps jtag_rclk 8 should be used, i.e. use RCLK if it is supported > and fall back to 8 khz. Of course post reset init jtag_rclk's fallback > frequency could be increased. jtalg_rclk 0
I think is better then If the board need to overwrite it the do it after the source of the soc file Best Regards, J. _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
