On Fri, May 6, 2011 at 10:33 AM, Jean-Christophe PLAGNIOL-VILLARD <plagn...@jcrosoft.com> wrote: > On 06:58 Fri 06 May , Ųyvind Harboe wrote: >> >> +# The chip may run @ 32khz, so set a really low JTAG speed >> >> +adapter_khz 8 >> > this is the wrong place it's not board specific but soc specific >> > >> > tcl/target/at91rm9200.cfg >> >> Perhaps jtag_rclk 8 should be used, i.e. use RCLK if it is supported >> and fall back to 8 khz. Of course post reset init jtag_rclk's fallback >> frequency could be increased. > jtalg_rclk 0
This illegal. jtag_rclk will use rclk, if rclk is available and fall back to the frequency specified. The above would mean "use rclk if available, otherwise 0khz" => error. I think using rclk if available and falling back to 8khz is a reasonable default. -- Øyvind Harboe Can Zylin Consulting help on your project? US toll free 1-866-980-3434 / International +47 51 87 40 27 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
