Ivan,
        With regard to your comments on the current carrying capability of a 
via. You forgot one factor, with everything perfect plating-wise the via 
typically will have approx. 1/2 - 2/3 the copper thickness/weight of a trace. 
This is dependant of course on the initial copper foil and plated Cu spec.. 
Then add in the typical restrictive nature of vias to plating and you will have 
a gotcha! The plating of a typical via will typically only be 35% - 50% copper 
weight of an external trace in real world practice.

        I'll wait for the usual snappy response, your coffee mustn't have 
kicked in yet this morning Ivan.

Sincerely,
Brad Velander
Senior PCB Designer
Northern Airborne Technology
1925 Kirschner Rd.,
Kelowna, BC, V1Y 4N7.
tel (250) 763-2329 ext. 225
fax (250) 762-3374


-----Original Message-----
From: Bagotronix Tech Support [mailto:[EMAIL PROTECTED]
Sent: August 2, 2005 9:47 AM
To: Protel EDA Discussion List
Subject: Re: [PEDA] Vias.


For Brad:
What is manufacturable depends on your fab house.  Every place (except the 
high volume super cheap fabs) should be able to do 18 mil hole with no 
price premium.  Some places go down to 13 mil with no premium.  As far as 
relationship to track widths, the effective width of the conductive 
material in the via is the via diameter * pi.  So, a 13 mil via has an 
equivalent track width of 13 * 3.14 = 41 mil.  That's wider than your 
tracks, so there should be no problems with current carrying capacity.  As 
far as pad size, the IPC rules (can't remember which one) state there 
should be a minimum of 2 mil annular ring around the hole.  You also need 
to account for misalignment of the drilled holes, due to drill machine 
tolerances.  Typically this is 5 mils.  Therefore, your annular ring as 
designed should be at least 7 mils.  And so, the via pad diameter ends up 
14 mils larger than the hole diameter.  For example, a 32 mil via pad with 
a 18 mil hole.

Best regards,
Ivan Baggett
Bagotronix Inc.
website:  www.bagotronix.com



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