Dennis,

I was just giving an example, not saying those are the minimum values possible.

Regards,
Igor

From: Dennis Saputelli <[EMAIL PROTECTED]>
Reply-To: Protel EDA Discussion List <[email protected]>
To: Protel EDA Discussion List <[email protected]>
Subject: Re: [PEDA] Vias.
Date: Thu, 04 Aug 2005 07:22:18 -0700

but Igor
i do 4 & 6 layer bds all the time at a local shop with 22 mil dia and 12 mil holes

they don't complain (or charge more as far as i know) and the holes are even well centered

and don't forget that 15 drill plates to 12 mil dia

but you are correct that 1 mil does make a big difference because when i tried to push him to 20/10 he said no!
(i know other shops will do this though)

Dennis Saputelli

PS
as an aside this same shop has what they call a 'direct image' printer (or some similar term, i forget exactly) for the 'silkscreen'
it is essentially a specialized inkjet printer
this allows the legend characters to go down to something like 32/4 (height/width in mils) as i remember and i think even smaller is possible w/ certain printers the appearance is a bit wimpy (the ink does not appear to be dense) but it is legible and goes where silkscreen never could

Dennis Saputelli

_______________________________________________________________________
Integrated Controls, Inc.           Tel: 415-647-0480  EXT 107
2851 21st Street                    Fax: 415-647-3003
San Francisco, CA 94110             www.integratedcontrolsinc.com


M P wrote:
One can find all that in the academic texts but they take two hundred pages to start explaining it. If someone explained that to me in a popular language in my early days, I would have enjoyed my university time much more. And if all theories were explained in such a way, it would take approximately one book for the whole four year course. So, Ivan get to work.

As for the vias, it mostly depends on the board manufacturers. Let's say their minimum whole size is 15mils (realistic value) and their specified minimum anular ring width is 8mils (again realistic value) that would result in 15mil + (2 x 8mil) = 31mil. You can either stick to their specs, or try to get down to 30mils and hope all goes well (not recommended), or add 1mil to the annular ring (trust no pcb manufacturer) and get 33mils overall diameter. 1mil means a lot on a pcb and can be a difference between making the board or not. I haven't seen any specific rules correlating the track width and the via diameter.

Igor

From: Mira <[EMAIL PROTECTED]>
Reply-To: Protel EDA Discussion List <[email protected]>
To: [EMAIL PROTECTED],Protel EDA Discussion List <[email protected]>
Subject: Re: [PEDA] Vias.
Date: Wed, 3 Aug 2005 13:22:55 -0700 (PDT)

It's very interesting how a simple "via/current"
question ended up with a theoretical explanation where
the current flows.
Ivan, you just killed all my basic engineering
knowledge. More than 25 years ago the theory was that
the current was a flow of the electrons but the
direction of the current is considered the opposite of
this flow i.e. from + to -.
Theory might have changed, who knows.

Now back to the "via" question.
Brad, contact your PCB manufacturer and check what is
the smallest via they feel happy with and what is the
plating thickness they guarantee.
Starting from there and knowing your layer structure
and PCB thickness you can calculate how much current
(maximum) will flow through this via. If this is
enough, use it. If this is not enough, use 2 vias or
use another hole size.
You may consider using blind vias or vias in pad if
the design is too dense but this depends also if your
fab can manufacture it.
The other thing (if you are allowed to do) is to
optimize the placement. Then you won't need to pass
the signal from layer to layer and this will save you
room for placing the traces.

Mira

--- Bagotronix Tech Support
<[EMAIL PROTECTED]> wrote:

> [EMAIL PROTECTED] wrote:
>  > And you both forgot that like water in a pipe,
> electrons will migrate to
>  > the side of the via in which the flow is
> occuring, further reducing the
>  > effective "trace width" of the via...
>
> I can't tell if aj is joking or serious...
>
> If we are going to use analogies to describe current
> flow, let's at least
> use correct ones.
>
> Current flow is the movement of electric charge
> through a medium.  The
> medium can be either conductive or non-conductive.
> If the medium is
> conductive, then you have "conduction current", as
> in current flowing
> through a wire.  If the medium is non-conductive,
> you have "displacement
> current", as in time-varying current flowing through
> the dielectric of a
> capacitor.
>
> Electric charge consists of positive or negative
> charges.  At the atomic
> level, a positive charge is an atom that is missing
> one or more electrons
> from it's electron orbitals.  The negative charge is
> a lone electron that
> has broken away from the orbital it was in, and is
> free to travel.  Where
> does it go?  It goes to the next electron-deficient
> atom it encounters.  It
> stays for a while, then hops to the next atom.  This
> process (electron
> drift) does not happen at the speed of light, as so
> many believe.  What
> does happen is that the electric field travels
> through the medium at nearly
> the speed of light (or some significant fraction
> thereof).  The actual
> electrons only travel a few meters per second.
>
> Here is the analogy that works:  you remember that
> novelty item with 5
> steel balls suspended in a row by threads?  You pull
> back one of the steel
> balls, let it go, and it swings back and hits the
> ball next to it.  The
> ball on the other end of the row swings out and then
> swings back, while the
> 3 inner balls stay stationary.  The silly thing
> keeps doing that
> "klak-klak" thing for a long time, until air
> resistance eventually robs it
> of the kinetic energy.  In this analogy, the 2 end
> balls are electrons, the
> three middle balls are the conductor, and the
> kinetic energy is the
> electric field.  Even though the end balls
> (electrons) are moving at only a
> some fraction of a meter per second, the speed at
> which the kinetic energy
> (electric field) is conducted through the middle
> balls (conductor) is much
> faster than that.
>
> So, the electrons will not pile up on a particular
> region of a via.  What
> you may be thinking of is "skin effect".  That
> happens when the electric
> field of a flowing current cannot penetrate equally
> through the depth of a
> conductor, and flows mostly on the surface of the
> conductor.  This effect
> becomes worse as you go higher in frequency.  It
> results in a reduction of
> the effective cross-sectional area of a conductor.
> If you want to think of
> that as electron migration to the surface of the
> conductor, that is a valid
> way to think of it.  Maybe that's what you had in
> mind.  Skin effect does
> not occur at DC, and is negligible at low
> frequencies in most cases.  It
> does become a concern in high-power switching power
> supplies and
> high-tension AC power transmission lines.
>
> One last item:  which way does current really flow?
>
> Answer:  it flows from where there are negative
> charges (electrons) to
> where there are positive charges (atoms missing an
> electron).  Therefore
> current does not really flow from + to -, as we
> commonly analyze our
> circuits.  Current actually flows from - to +.  So
> why does our stuff work?
>   Because unless you are working with the actual
> physics of semiconductors
> and materials, it doesn't really matter which way
> the current flows, as
> long as you choose one direction and stick with it.
> What most of us EE's
> (myself included) use is called "convential flow",
> which is + to -, but is
> incorrect theoretically.  Some EE's use "electron
> flow", which is - to +,
> and is correct theoretically.
>
> Put that in your academic pipe and smoke it   ;-)
>
> Best regards,
> Ivan Baggett
> Bagotronix Inc.
> website:  www.bagotronix.com
>
>
> [EMAIL PROTECTED] wrote:
> > And you both forgot that like water in a pipe,
> electrons will migrate to
> > the side of the via in which the flow is occuring,
> further reducing the
> > effective "trace width" of the via...
> >
> > aj
>
>
>
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