> Greetings All, > Can anyone direct me to information on the relationship between copper > area and thermal impedance for SMD devices?
> I have a D2PAK MOSFET that has a Thermal impedance of 40K/W junction to > ambient when mounted with a minimum of copper on the mounting tab.. > I'd like to reduce this figure by adding a copper area (polygon or fill) > to the mounting tab. > The problem is I don't have a feel for how much copper is needed for a > particular reduction in thermal impedance. > Thanks in advance, > Linden Doyle Linden, This application note from Philips gives some relevant information http://www.semiconductors.philips.com/acrobat_download/applicationnotes/AN_SM_T_AND_T.pdf Regards David ____________________________________________________________ You are subscribed to the PEDA discussion forum To Post messages: mailto:[email protected] Unsubscribe and Other Options: http://techservinc.com/mailman/listinfo/peda_techservinc.com Browse or Search Old Archives (2001-2004): http://www.mail-archive.com/[email protected] Browse or Search Current Archives (2004-Current): http://www.mail-archive.com/[email protected]
